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[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
This matches gcc. It also lets us fix a bug that the byteselect predicate was not being evaluated in tablegen. We can't have i8 TImmLeaf in tablegen because i8 isn't a type for any register class. I've added AutoUpgrade support for the IR intrinsics. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D152627
1 parent 335c0f7 commit 2f2af2d

16 files changed

+195
-35
lines changed

‎clang/include/clang/Basic/BuiltinsRISCV.def

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
3838
TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
3939

4040
// Zknd extension
41-
TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
42-
TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
41+
TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUi", "nc", "zknd,32bit")
42+
TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUi", "nc", "zknd,32bit")
4343
TARGET_BUILTIN(__builtin_riscv_aes64ds_64, "WiWiWi", "nc", "zknd,64bit")
4444
TARGET_BUILTIN(__builtin_riscv_aes64dsm_64, "WiWiWi", "nc", "zknd,64bit")
4545
TARGET_BUILTIN(__builtin_riscv_aes64im_64, "WiWi", "nc", "zknd,64bit")
@@ -49,8 +49,8 @@ TARGET_BUILTIN(__builtin_riscv_aes64ks1i_64, "WiWiIUi", "nc", "zknd|zkne,64bit")
4949
TARGET_BUILTIN(__builtin_riscv_aes64ks2_64, "WiWiWi", "nc", "zknd|zkne,64bit")
5050

5151
// Zkne extension
52-
TARGET_BUILTIN(__builtin_riscv_aes32esi_32, "ZiZiZiIUc", "nc", "zkne,32bit")
53-
TARGET_BUILTIN(__builtin_riscv_aes32esmi_32, "ZiZiZiIUc", "nc", "zkne,32bit")
52+
TARGET_BUILTIN(__builtin_riscv_aes32esi_32, "ZiZiZiIUi", "nc", "zkne,32bit")
53+
TARGET_BUILTIN(__builtin_riscv_aes32esmi_32, "ZiZiZiIUi", "nc", "zkne,32bit")
5454
TARGET_BUILTIN(__builtin_riscv_aes64es_64, "WiWiWi", "nc", "zkne,64bit")
5555
TARGET_BUILTIN(__builtin_riscv_aes64esm_64, "WiWiWi", "nc", "zkne,64bit")
5656

@@ -72,8 +72,8 @@ TARGET_BUILTIN(__builtin_riscv_sha512sum0_64, "WiWi", "nc", "zknh,64bit")
7272
TARGET_BUILTIN(__builtin_riscv_sha512sum1_64, "WiWi", "nc", "zknh,64bit")
7373

7474
// Zksed extension
75-
TARGET_BUILTIN(__builtin_riscv_sm4ed, "LiLiLiIUc", "nc", "zksed")
76-
TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUc", "nc", "zksed")
75+
TARGET_BUILTIN(__builtin_riscv_sm4ed, "LiLiLiIUi", "nc", "zksed")
76+
TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUi", "nc", "zksed")
7777

7878
// Zksh extension
7979
TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "zksh")

‎clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// RV32ZKND-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
1111
// RV32ZKND-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
1212
// RV32ZKND-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
13-
// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
13+
// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
1414
// RV32ZKND-NEXT: ret i32 [[TMP2]]
1515
//
1616
int aes32dsi(int rs1, int rs2) {
@@ -25,7 +25,7 @@ int aes32dsi(int rs1, int rs2) {
2525
// RV32ZKND-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
2626
// RV32ZKND-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
2727
// RV32ZKND-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
28-
// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
28+
// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
2929
// RV32ZKND-NEXT: ret i32 [[TMP2]]
3030
//
3131
int aes32dsmi(int rs1, int rs2) {

‎clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
1111
// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
1212
// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
13-
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
13+
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
1414
// RV32ZKNE-NEXT: ret i32 [[TMP2]]
1515
//
1616
int aes32esi(int rs1, int rs2) {
@@ -25,7 +25,7 @@ int aes32esi(int rs1, int rs2) {
2525
// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
2626
// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
2727
// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
28-
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
28+
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esmi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
2929
// RV32ZKNE-NEXT: ret i32 [[TMP2]]
3030
//
3131
int aes32esmi(int rs1, int rs2) {

‎clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// RV32ZKSED-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
1111
// RV32ZKSED-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
1212
// RV32ZKSED-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
13-
// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
13+
// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks.i32(i32 [[TMP0]], i32 [[TMP1]], i32 0)
1414
// RV32ZKSED-NEXT: ret i32 [[TMP2]]
1515
//
1616
long sm4ks(long rs1, long rs2) {
@@ -26,7 +26,7 @@ long sm4ks(long rs1, long rs2) {
2626
// RV32ZKSED-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
2727
// RV32ZKSED-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
2828
// RV32ZKSED-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
29-
// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
29+
// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed.i32(i32 [[TMP0]], i32 [[TMP1]], i32 0)
3030
// RV32ZKSED-NEXT: ret i32 [[TMP2]]
3131
//
3232
long sm4ed(long rs1, long rs2) {

‎clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// RV64ZKSED-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
1111
// RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
1212
// RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
13-
// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ks.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
13+
// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ks.i64(i64 [[TMP0]], i64 [[TMP1]], i32 0)
1414
// RV64ZKSED-NEXT: ret i64 [[TMP2]]
1515
//
1616
long sm4ks(long rs1, long rs2) {
@@ -25,7 +25,7 @@ long sm4ks(long rs1, long rs2) {
2525
// RV64ZKSED-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
2626
// RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
2727
// RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
28-
// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ed.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
28+
// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ed.i64(i64 [[TMP0]], i64 [[TMP1]], i32 0)
2929
// RV64ZKSED-NEXT: ret i64 [[TMP2]]
3030
//
3131
long sm4ed(long rs1, long rs2) {

‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1511,7 +1511,7 @@ class ScalarCryptoGprIntrinsicAny
15111511

15121512
class ScalarCryptoByteSelect32
15131513
: DefaultAttrsIntrinsic<[llvm_i32_ty],
1514-
[llvm_i32_ty, llvm_i32_ty, llvm_i8_ty],
1514+
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
15151515
[IntrNoMem, IntrSpeculatable,
15161516
ImmArg<ArgIndex<2>>]>;
15171517

@@ -1532,7 +1532,7 @@ class ScalarCryptoGprIntrinsic64
15321532

15331533
class ScalarCryptoByteSelectAny
15341534
: DefaultAttrsIntrinsic<[llvm_anyint_ty],
1535-
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i8_ty],
1535+
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
15361536
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
15371537

15381538
// Zknd

‎llvm/lib/IR/AutoUpgrade.cpp

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include "llvm/IR/Intrinsics.h"
2929
#include "llvm/IR/IntrinsicsAArch64.h"
3030
#include "llvm/IR/IntrinsicsARM.h"
31+
#include "llvm/IR/IntrinsicsRISCV.h"
3132
#include "llvm/IR/IntrinsicsWebAssembly.h"
3233
#include "llvm/IR/IntrinsicsX86.h"
3334
#include "llvm/IR/LLVMContext.h"
@@ -1127,6 +1128,47 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
11271128
}
11281129
break;
11291130

1131+
case 'r':
1132+
if (Name == "riscv.aes32dsi" &&
1133+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1134+
rename(F);
1135+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_aes32dsi);
1136+
return true;
1137+
}
1138+
if (Name == "riscv.aes32dsmi" &&
1139+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1140+
rename(F);
1141+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_aes32dsmi);
1142+
return true;
1143+
}
1144+
if (Name == "riscv.aes32esi" &&
1145+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1146+
rename(F);
1147+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_aes32esi);
1148+
return true;
1149+
}
1150+
if (Name == "riscv.aes32esmi" &&
1151+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1152+
rename(F);
1153+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_aes32esmi);
1154+
return true;
1155+
}
1156+
if (Name.startswith("riscv.sm4ks") &&
1157+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1158+
rename(F);
1159+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_sm4ks,
1160+
F->getReturnType());
1161+
return true;
1162+
}
1163+
if (Name.startswith("riscv.sm4ed") &&
1164+
!F->getFunctionType()->getParamType(2)->isIntegerTy(32)) {
1165+
rename(F);
1166+
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::riscv_sm4ed,
1167+
F->getReturnType());
1168+
return true;
1169+
}
1170+
break;
1171+
11301172
case 's':
11311173
if (Name == "stackprotectorcheck") {
11321174
NewFn = nullptr;
@@ -4236,6 +4278,24 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) {
42364278
CI->eraseFromParent();
42374279
return;
42384280

4281+
case Intrinsic::riscv_aes32dsi:
4282+
case Intrinsic::riscv_aes32dsmi:
4283+
case Intrinsic::riscv_aes32esi:
4284+
case Intrinsic::riscv_aes32esmi:
4285+
case Intrinsic::riscv_sm4ks:
4286+
case Intrinsic::riscv_sm4ed: {
4287+
// The last argument to these intrinsics used to be i8 and changed to i32.
4288+
Value *Arg2 = CI->getArgOperand(2);
4289+
if (Arg2->getType()->isIntegerTy(32))
4290+
return;
4291+
4292+
Arg2 = ConstantInt::get(Type::getInt32Ty(C), cast<ConstantInt>(Arg2)->getZExtValue());
4293+
4294+
NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0),
4295+
CI->getArgOperand(1), Arg2});
4296+
break;
4297+
}
4298+
42394299
case Intrinsic::x86_xop_vfrcz_ss:
42404300
case Intrinsic::x86_xop_vfrcz_sd:
42414301
NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)});

‎llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ def rnum : Operand<i32>, TImmLeaf<i32, [{return (Imm >= 0 && Imm <= 10);}]> {
2929
let OperandNamespace = "RISCVOp";
3030
}
3131

32-
def byteselect : Operand<i8>, TImmLeaf<i8, [{return isUInt<2>(Imm);}]> {
32+
def byteselect : Operand<i32>, TImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
3333
let ParserMatchClass = UImmAsmOperand<2>;
3434
let DecoderMethod = "decodeUImmOperand<2>";
3535
let OperandType = "OPERAND_UIMM2";
@@ -134,7 +134,7 @@ def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">;
134134
//===----------------------------------------------------------------------===//
135135

136136
class PatGprGprByteSelect<SDPatternOperator OpNode, RVInst Inst>
137-
: Pat<(OpNode GPR:$rs1, GPR:$rs2, i8:$imm),
137+
: Pat<(OpNode GPR:$rs1, GPR:$rs2, byteselect:$imm),
138138
(Inst GPR:$rs1, GPR:$rs2, byteselect:$imm)>;
139139

140140
// Zknd
@@ -151,7 +151,7 @@ def : PatGpr<int_riscv_aes64im, AES64IM>;
151151

152152
let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
153153
def : PatGprGpr<int_riscv_aes64ks2, AES64KS2>;
154-
def : Pat<(int_riscv_aes64ks1i GPR:$rs1, i32:$rnum),
154+
def : Pat<(int_riscv_aes64ks1i GPR:$rs1, rnum:$rnum),
155155
(AES64KS1I GPR:$rs1, rnum:$rnum)>;
156156
} // Predicates = [HasStdExtZkndOrZkne, IsRV64]
157157

‎llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+zknd -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV32ZKND
4+
5+
declare i32 @llvm.riscv.aes32dsi(i32, i32, i8);
6+
7+
define i32 @aes32dsi(i32 %a, i32 %b) nounwind {
8+
; RV32ZKND-LABEL: aes32dsi:
9+
; RV32ZKND: # %bb.0:
10+
; RV32ZKND-NEXT: aes32dsi a0, a0, a1, 0
11+
; RV32ZKND-NEXT: ret
12+
%val = call i32 @llvm.riscv.aes32dsi(i32 %a, i32 %b, i8 0)
13+
ret i32 %val
14+
}
15+
16+
declare i32 @llvm.riscv.aes32dsmi(i32, i32, i8);
17+
18+
define i32 @aes32dsmi(i32 %a, i32 %b) nounwind {
19+
; RV32ZKND-LABEL: aes32dsmi:
20+
; RV32ZKND: # %bb.0:
21+
; RV32ZKND-NEXT: aes32dsmi a0, a0, a1, 1
22+
; RV32ZKND-NEXT: ret
23+
%val = call i32 @llvm.riscv.aes32dsmi(i32 %a, i32 %b, i8 1)
24+
ret i32 %val
25+
}

‎llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,24 +2,24 @@
22
; RUN: llc -mtriple=riscv32 -mattr=+zknd -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefix=RV32ZKND
44

5-
declare i32 @llvm.riscv.aes32dsi(i32, i32, i8);
5+
declare i32 @llvm.riscv.aes32dsi(i32, i32, i32);
66

77
define i32 @aes32dsi(i32 %a, i32 %b) nounwind {
88
; RV32ZKND-LABEL: aes32dsi:
99
; RV32ZKND: # %bb.0:
1010
; RV32ZKND-NEXT: aes32dsi a0, a0, a1, 0
1111
; RV32ZKND-NEXT: ret
12-
%val = call i32 @llvm.riscv.aes32dsi(i32 %a, i32 %b, i8 0)
12+
%val = call i32 @llvm.riscv.aes32dsi(i32 %a, i32 %b, i32 0)
1313
ret i32 %val
1414
}
1515

16-
declare i32 @llvm.riscv.aes32dsmi(i32, i32, i8);
16+
declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32);
1717

1818
define i32 @aes32dsmi(i32 %a, i32 %b) nounwind {
1919
; RV32ZKND-LABEL: aes32dsmi:
2020
; RV32ZKND: # %bb.0:
2121
; RV32ZKND-NEXT: aes32dsmi a0, a0, a1, 1
2222
; RV32ZKND-NEXT: ret
23-
%val = call i32 @llvm.riscv.aes32dsmi(i32 %a, i32 %b, i8 1)
23+
%val = call i32 @llvm.riscv.aes32dsmi(i32 %a, i32 %b, i32 1)
2424
ret i32 %val
2525
}

‎llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+zkne -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV32ZKNE
4+
5+
declare i32 @llvm.riscv.aes32esi(i32, i32, i8);
6+
7+
define i32 @aes32esi(i32 %a, i32 %b) nounwind {
8+
; RV32ZKNE-LABEL: aes32esi:
9+
; RV32ZKNE: # %bb.0:
10+
; RV32ZKNE-NEXT: aes32esi a0, a0, a1, 2
11+
; RV32ZKNE-NEXT: ret
12+
%val = call i32 @llvm.riscv.aes32esi(i32 %a, i32 %b, i8 2)
13+
ret i32 %val
14+
}
15+
16+
declare i32 @llvm.riscv.aes32esmi(i32, i32, i8);
17+
18+
define i32 @aes32esmi(i32 %a, i32 %b) nounwind {
19+
; RV32ZKNE-LABEL: aes32esmi:
20+
; RV32ZKNE: # %bb.0:
21+
; RV32ZKNE-NEXT: aes32esmi a0, a0, a1, 3
22+
; RV32ZKNE-NEXT: ret
23+
%val = call i32 @llvm.riscv.aes32esmi(i32 %a, i32 %b, i8 3)
24+
ret i32 %val
25+
}

‎llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,24 +2,24 @@
22
; RUN: llc -mtriple=riscv32 -mattr=+zkne -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefix=RV32ZKNE
44

5-
declare i32 @llvm.riscv.aes32esi(i32, i32, i8);
5+
declare i32 @llvm.riscv.aes32esi(i32, i32, i32);
66

77
define i32 @aes32esi(i32 %a, i32 %b) nounwind {
88
; RV32ZKNE-LABEL: aes32esi:
99
; RV32ZKNE: # %bb.0:
1010
; RV32ZKNE-NEXT: aes32esi a0, a0, a1, 2
1111
; RV32ZKNE-NEXT: ret
12-
%val = call i32 @llvm.riscv.aes32esi(i32 %a, i32 %b, i8 2)
12+
%val = call i32 @llvm.riscv.aes32esi(i32 %a, i32 %b, i32 2)
1313
ret i32 %val
1414
}
1515

16-
declare i32 @llvm.riscv.aes32esmi(i32, i32, i8);
16+
declare i32 @llvm.riscv.aes32esmi(i32, i32, i32);
1717

1818
define i32 @aes32esmi(i32 %a, i32 %b) nounwind {
1919
; RV32ZKNE-LABEL: aes32esmi:
2020
; RV32ZKNE: # %bb.0:
2121
; RV32ZKNE-NEXT: aes32esmi a0, a0, a1, 3
2222
; RV32ZKNE-NEXT: ret
23-
%val = call i32 @llvm.riscv.aes32esmi(i32 %a, i32 %b, i8 3)
23+
%val = call i32 @llvm.riscv.aes32esmi(i32 %a, i32 %b, i32 3)
2424
ret i32 %val
2525
}

‎llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+zksed -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV32ZKSED
4+
5+
declare i32 @llvm.riscv.sm4ks.i32(i32, i32, i8);
6+
7+
define i32 @sm4ks_i32(i32 %a, i32 %b) nounwind {
8+
; RV32ZKSED-LABEL: sm4ks_i32:
9+
; RV32ZKSED: # %bb.0:
10+
; RV32ZKSED-NEXT: sm4ks a0, a0, a1, 2
11+
; RV32ZKSED-NEXT: ret
12+
%val = call i32 @llvm.riscv.sm4ks.i32(i32 %a, i32 %b, i8 2)
13+
ret i32 %val
14+
}
15+
16+
declare i32 @llvm.riscv.sm4ed.i32(i32, i32, i8);
17+
18+
define i32 @sm4ed_i32(i32 %a, i32 %b) nounwind {
19+
; RV32ZKSED-LABEL: sm4ed_i32:
20+
; RV32ZKSED: # %bb.0:
21+
; RV32ZKSED-NEXT: sm4ed a0, a0, a1, 3
22+
; RV32ZKSED-NEXT: ret
23+
%val = call i32 @llvm.riscv.sm4ed.i32(i32 %a, i32 %b, i8 3)
24+
ret i32 %val
25+
}

‎llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,24 +2,24 @@
22
; RUN: llc -mtriple=riscv32 -mattr=+zksed -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefix=RV32ZKSED
44

5-
declare i32 @llvm.riscv.sm4ks.i32(i32, i32, i8);
5+
declare i32 @llvm.riscv.sm4ks.i32(i32, i32, i32);
66

77
define i32 @sm4ks_i32(i32 %a, i32 %b) nounwind {
88
; RV32ZKSED-LABEL: sm4ks_i32:
99
; RV32ZKSED: # %bb.0:
1010
; RV32ZKSED-NEXT: sm4ks a0, a0, a1, 2
1111
; RV32ZKSED-NEXT: ret
12-
%val = call i32 @llvm.riscv.sm4ks.i32(i32 %a, i32 %b, i8 2)
12+
%val = call i32 @llvm.riscv.sm4ks.i32(i32 %a, i32 %b, i32 2)
1313
ret i32 %val
1414
}
1515

16-
declare i32 @llvm.riscv.sm4ed.i32(i32, i32, i8);
16+
declare i32 @llvm.riscv.sm4ed.i32(i32, i32, i32);
1717

1818
define i32 @sm4ed_i32(i32 %a, i32 %b) nounwind {
1919
; RV32ZKSED-LABEL: sm4ed_i32:
2020
; RV32ZKSED: # %bb.0:
2121
; RV32ZKSED-NEXT: sm4ed a0, a0, a1, 3
2222
; RV32ZKSED-NEXT: ret
23-
%val = call i32 @llvm.riscv.sm4ed.i32(i32 %a, i32 %b, i8 3)
23+
%val = call i32 @llvm.riscv.sm4ed.i32(i32 %a, i32 %b, i32 3)
2424
ret i32 %val
2525
}

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