[MLIR][SPIRV] Rename spv._module_end to spv.mlir.endmodule

This commit does the renaming mentioned in the title in order to bring
'spv' dialect closer to the MLIR naming conventions.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D91792

Author: ergawy

mlir/docs/Dialects/SPIR-V.md

@@ -92,7 +92,7 @@ The SPIR-V dialect adopts the following conventions for IR:
     (de)serialization.
 *   Ops with `mlir.snake_case` names are those that have no corresponding
     instructions (or concepts) in the binary format. They are introduced to
-    satisfy MLIR structural requirements. For example, `spv.mlir.module_end` and
+    satisfy MLIR structural requirements. For example, `spv.mlir.endmodule` and
     `spv.mlir.merge`. They map to no instructions during (de)serialization.
 
 (TODO: consider merging the last two cases and adopting `spv.mlir.` prefix for

mlir/docs/SPIRVToLLVMDialectConversion.md

@@ -787,7 +787,7 @@ Module in SPIR-V has one region that contains one block. It is defined via
 `spv.module` is converted into `ModuleOp`. This plays a role of enclosing scope
 to LLVM ops. At the moment, SPIR-V module attributes are ignored.
 
-`spv._module_end` is mapped to an equivalent terminator `ModuleTerminatorOp`.
+`spv.mlir.endmodule` is mapped to an equivalent terminator `ModuleTerminatorOp`.
 
 ## `mlir-spirv-cpu-runner`
 

mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td

@@ -373,7 +373,7 @@ def SPV_ModuleOp : SPV_Op<"module",
     implicitly capture values from the enclosing environment.
 
     This op has only one region, which only contains one block. The block
-    must be terminated via the `spv._module_end` op.
+    must be terminated via the `spv.mlir.endmodule` op.
 
     <!-- End of AutoGen section -->
 
@@ -443,7 +443,7 @@ def SPV_ModuleOp : SPV_Op<"module",
 
 // -----
 
-def SPV_ModuleEndOp : SPV_Op<"_module_end", [InModuleScope, Terminator]> {
+def SPV_ModuleEndOp : SPV_Op<"mlir.endmodule", [InModuleScope, Terminator]> {
   let summary = "The pseudo op that ends a SPIR-V module";
 
   let description = [{

mlir/test/Conversion/SPIRVToLLVM/module-ops-to-llvm.mlir

@@ -16,7 +16,7 @@ spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], [SPV_KHR_16bit_stor
 // CHECK: module
 spv.module Logical GLSL450 {
 	// CHECK: }
-  spv._module_end
+  spv.mlir.endmodule
 }
 
 // CHECK: module

mlir/test/Dialect/SPIRV/structure-ops.mlir

@@ -390,10 +390,10 @@ spv.module Logical GLSL450
   requires #spv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]>
   attributes {foo = "bar"} { }
 
-// Module with explicit spv._module_end
+// Module with explicit spv.mlir.endmodule
 // CHECK: spv.module
 spv.module Logical GLSL450 {
-  spv._module_end
+  spv.mlir.endmodule
 }
 
 // Module with function
@@ -442,8 +442,8 @@ spv.module Logical GLSL450 {
 // -----
 
 // Module with wrong terminator
-// expected-error@+2 {{expects regions to end with 'spv._module_end'}}
-// expected-note@+1 {{in custom textual format, the absence of terminator implies 'spv._module_end'}}
+// expected-error@+2 {{expects regions to end with 'spv.mlir.endmodule'}}
+// expected-note@+1 {{in custom textual format, the absence of terminator implies 'spv.mlir.endmodule'}}
 "spv.module"() ({
   %0 = spv.constant true
 }) {addressing_model = 0 : i32, memory_model = 1 : i32} : () -> ()
@@ -477,12 +477,12 @@ spv.module Logical GLSL450 {
 // -----
 
 //===----------------------------------------------------------------------===//
-// spv._module_end
+// spv.mlir.endmodule
 //===----------------------------------------------------------------------===//
 
 func @module_end_not_in_module() -> () {
   // expected-error @+1 {{op must appear in a module-like op's block}}
-  spv._module_end
+  spv.mlir.endmodule
 }
 
 // -----