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Merge pull request #9105 from citymarina/csel-cherry-pick
[AArch64] Cherry-pick fix for redundant csel instructions
2 parents ddcb446 + ad330d7 commit 33b00bb

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‎llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp

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Original file line numberDiff line numberDiff line change
@@ -61,6 +61,9 @@
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// %6:fpr128 = IMPLICIT_DEF
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// %7:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub
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//
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// 8. Remove redundant CSELs that select between identical registers, by
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// replacing them with unconditional moves.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64ExpandImm.h"
@@ -124,6 +127,7 @@ struct AArch64MIPeepholeOpt : public MachineFunctionPass {
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template <typename T>
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bool visitAND(unsigned Opc, MachineInstr &MI);
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bool visitORR(MachineInstr &MI);
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bool visitCSEL(MachineInstr &MI);
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bool visitINSERT(MachineInstr &MI);
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bool visitINSviGPR(MachineInstr &MI, unsigned Opc);
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bool visitINSvi64lane(MachineInstr &MI);
@@ -283,6 +287,26 @@ bool AArch64MIPeepholeOpt::visitORR(MachineInstr &MI) {
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return true;
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}
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bool AArch64MIPeepholeOpt::visitCSEL(MachineInstr &MI) {
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// Replace CSEL with MOV when both inputs are the same register.
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if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg())
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return false;
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auto ZeroReg =
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MI.getOpcode() == AArch64::CSELXr ? AArch64::XZR : AArch64::WZR;
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auto OrOpcode =
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MI.getOpcode() == AArch64::CSELXr ? AArch64::ORRXrs : AArch64::ORRWrs;
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BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(OrOpcode))
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.addReg(MI.getOperand(0).getReg(), RegState::Define)
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.addReg(ZeroReg)
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.addReg(MI.getOperand(1).getReg())
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.addImm(0);
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MI.eraseFromParent();
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return true;
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}
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bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) {
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// Check this INSERT_SUBREG comes from below zero-extend pattern.
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//
@@ -788,6 +812,10 @@ bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
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visitADDSSUBS<uint64_t>({AArch64::SUBXri, AArch64::SUBSXri},
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{AArch64::ADDXri, AArch64::ADDSXri}, MI);
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break;
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case AArch64::CSELWr:
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case AArch64::CSELXr:
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Changed |= visitCSEL(MI);
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break;
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case AArch64::INSvi64gpr:
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Changed |= visitINSviGPR(MI, AArch64::INSvi64lane);
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break;

‎llvm/test/CodeGen/AArch64/peephole-csel.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define void @peephole_csel(ptr %dst, i1 %0, i1 %cmp) {
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; CHECK-LABEL: peephole_csel:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: mov x9, xzr
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; CHECK-NEXT: tst w1, #0x1
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; CHECK-NEXT: csel x8, x8, x9, eq
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; CHECK-NEXT: str x8, [x0]
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; CHECK-NEXT: ret
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entry:
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br i1 %0, label %then, label %exit
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then: ; preds = %entry
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; The donothing() is needed to make make this block less interesting to
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; SimplifyCFG. Otherwise we may not get the csel that we want to test.
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call void @llvm.donothing()
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br i1 %cmp, label %true, label %exit
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true: ; preds = %then
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; Same as above
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call void @llvm.donothing()
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br label %exit
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exit: ; preds = %true, %then, %entry
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%x = phi i64 [ 0, %true ], [ 0, %then ], [ 1, %entry ]
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store i64 %x, ptr %dst, align 8
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ret void
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}

‎llvm/test/CodeGen/AArch64/peephole-csel.mir

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s
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---
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name: peephole_cselxr_same
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registers:
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- { id: 1, class: gpr64, preferred-register: '' }
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- { id: 2, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%1' }
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- { reg: '$x1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: peephole_cselxr_same
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[ORRXrs:%[0-9]+]]:gpr64 = ORRXrs $xzr, [[COPY1]], 0
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr64 = COPY $x1
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%4:gpr64 = COPY $x0
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$xzr = ANDSXri %3, 0, implicit-def $nzcv
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%5:gpr64 = CSELXr %4, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselwr_same
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registers:
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$w0', virtual-reg: '%1' }
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- { reg: '$w1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: peephole_cselwr_same
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY1]], 0
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr32 = COPY $w1
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%4:gpr32 = COPY $w0
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$wzr = ANDSWri %3, 0, implicit-def $nzcv
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%5:gpr32 = CSELWr %4, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselxr_different
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registers:
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- { id: 1, class: gpr64, preferred-register: '' }
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- { id: 2, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%1' }
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- { reg: '$x1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: peephole_cselxr_different
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr64 = COPY $x1
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%4:gpr64 = COPY $x0
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$xzr = ANDSXri %3, 0, implicit-def $nzcv
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%5:gpr64 = CSELXr %3, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselwr_different
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registers:
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$w0', virtual-reg: '%1' }
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- { reg: '$w1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: peephole_cselwr_different
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr32 = COPY $w1
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%4:gpr32 = COPY $w0
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$wzr = ANDSWri %3, 0, implicit-def $nzcv
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%5:gpr32 = CSELWr %3, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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