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[InstCombine] Fold (-a >> b) and/or/xor (~a >> b) into (-a and/or/xor ~a) >> b
Fold (-a >> b) and/or/xor (~a >> b) into (-a and/or/xor ~a) >> b. Depends on D157289. Differential Revision: https://reviews.llvm.org/D157290
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-58
lines changed

2 files changed

+69
-58
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‎llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,14 @@ static Value *tryFactorization(BinaryOperator &I, const SimplifyQuery &SQ,
751751
// 2) BinOp1 == BinOp2 (if BinOp == `add`, then also requires `shl`).
752752
//
753753
// -> (BinOp (logic_shift (BinOp X, Y)), Mask)
754+
//
755+
// (Binop1 (Binop2 (arithmetic_shift X, Amt), Mask), (arithmetic_shift Y, Amt))
756+
// IFF
757+
// 1) Binop1 is bitwise logical operator `and`, `or` or `xor`
758+
// 2) Binop2 is `not`
759+
//
760+
// -> (arithmetic_shift Binop1((not X), Y), Amt)
761+
754762
Instruction *InstCombinerImpl::foldBinOpShiftWithShift(BinaryOperator &I) {
755763
auto IsValidBinOpc = [](unsigned Opc) {
756764
switch (Opc) {
@@ -770,11 +778,13 @@ Instruction *InstCombinerImpl::foldBinOpShiftWithShift(BinaryOperator &I) {
770778
// constraints.
771779
auto IsCompletelyDistributable = [](unsigned BinOpc1, unsigned BinOpc2,
772780
unsigned ShOpc) {
781+
assert(ShOpc != Instruction::AShr);
773782
return (BinOpc1 != Instruction::Add && BinOpc2 != Instruction::Add) ||
774783
ShOpc == Instruction::Shl;
775784
};
776785

777786
auto GetInvShift = [](unsigned ShOpc) {
787+
assert(ShOpc != Instruction::AShr);
778788
return ShOpc == Instruction::LShr ? Instruction::Shl : Instruction::LShr;
779789
};
780790

@@ -807,14 +817,13 @@ Instruction *InstCombinerImpl::foldBinOpShiftWithShift(BinaryOperator &I) {
807817
Constant *CMask, *CShift;
808818
Value *X, *Y, *ShiftedX, *Mask, *Shift;
809819
if (!match(I.getOperand(ShOpnum),
810-
m_OneUse(m_LogicalShift(m_Value(Y), m_Value(Shift)))))
820+
m_OneUse(m_Shift(m_Value(Y), m_Value(Shift)))))
811821
return nullptr;
812822
if (!match(I.getOperand(1 - ShOpnum),
813823
m_BinOp(m_Value(ShiftedX), m_Value(Mask))))
814824
return nullptr;
815825

816-
if (!match(ShiftedX,
817-
m_OneUse(m_LogicalShift(m_Value(X), m_Specific(Shift)))))
826+
if (!match(ShiftedX, m_OneUse(m_Shift(m_Value(X), m_Specific(Shift)))))
818827
return nullptr;
819828

820829
// Make sure we are matching instruction shifts and not ConstantExpr
@@ -838,6 +847,18 @@ Instruction *InstCombinerImpl::foldBinOpShiftWithShift(BinaryOperator &I) {
838847
if (!IsValidBinOpc(I.getOpcode()) || !IsValidBinOpc(BinOpc))
839848
return nullptr;
840849

850+
if (ShOpc == Instruction::AShr) {
851+
if (Instruction::isBitwiseLogicOp(I.getOpcode()) &&
852+
BinOpc == Instruction::Xor && match(Mask, m_AllOnes())) {
853+
Value *NotX = Builder.CreateNot(X);
854+
Value *NewBinOp = Builder.CreateBinOp(I.getOpcode(), Y, NotX);
855+
return BinaryOperator::Create(
856+
static_cast<Instruction::BinaryOps>(ShOpc), NewBinOp, Shift);
857+
}
858+
859+
return nullptr;
860+
}
861+
841862
// If BinOp1 == BinOp2 and it's bitwise or shl with add, then just
842863
// distribute to drop the shift irrelevant of constants.
843864
if (BinOpc == I.getOpcode() &&

‎llvm/test/Transforms/InstCombine/binop-and-shifts.ll

Lines changed: 45 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -554,10 +554,9 @@ define i8 @shl_add_and_fail_mismatch_shift(i8 %x, i8 %y) {
554554

555555
define i8 @and_ashr_not(i8 %x, i8 %y, i8 %shamt) {
556556
; CHECK-LABEL: @and_ashr_not(
557-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr i8 [[X:%.*]], [[SHAMT:%.*]]
558-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr i8 [[Y:%.*]], [[SHAMT]]
559-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor i8 [[Y_SHIFT]], -1
560-
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X_SHIFT]], [[Y_SHIFT_NOT]]
557+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
558+
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
559+
; CHECK-NEXT: [[AND:%.*]] = ashr i8 [[TMP2]], [[SHAMT:%.*]]
561560
; CHECK-NEXT: ret i8 [[AND]]
562561
;
563562
%x.shift = ashr i8 %x, %shamt
@@ -569,10 +568,9 @@ define i8 @and_ashr_not(i8 %x, i8 %y, i8 %shamt) {
569568

570569
define i8 @and_ashr_not_commuted(i8 %x, i8 %y, i8 %shamt) {
571570
; CHECK-LABEL: @and_ashr_not_commuted(
572-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr i8 [[X:%.*]], [[SHAMT:%.*]]
573-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr i8 [[Y:%.*]], [[SHAMT]]
574-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor i8 [[Y_SHIFT]], -1
575-
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X_SHIFT]], [[Y_SHIFT_NOT]]
571+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
572+
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
573+
; CHECK-NEXT: [[AND:%.*]] = ashr i8 [[TMP2]], [[SHAMT:%.*]]
576574
; CHECK-NEXT: ret i8 [[AND]]
577575
;
578576
%x.shift = ashr i8 %x, %shamt
@@ -635,10 +633,9 @@ define i8 @and_ashr_not_fail_invalid_xor_constant(i8 %x, i8 %y, i8 %shamt) {
635633

636634
define <4 x i8> @and_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
637635
; CHECK-LABEL: @and_ashr_not_vec(
638-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
639-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
640-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 -1, i8 -1, i8 -1>
641-
; CHECK-NEXT: [[AND:%.*]] = and <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
636+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
637+
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i8> [[TMP1]], [[X:%.*]]
638+
; CHECK-NEXT: [[AND:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
642639
; CHECK-NEXT: ret <4 x i8> [[AND]]
643640
;
644641
%x.shift = ashr <4 x i8> %x, %shamt
@@ -650,10 +647,9 @@ define <4 x i8> @and_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
650647

651648
define <4 x i8> @and_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
652649
; CHECK-LABEL: @and_ashr_not_vec_commuted(
653-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
654-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
655-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 -1, i8 -1, i8 -1>
656-
; CHECK-NEXT: [[AND:%.*]] = and <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
650+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
651+
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i8> [[TMP1]], [[X:%.*]]
652+
; CHECK-NEXT: [[AND:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
657653
; CHECK-NEXT: ret <4 x i8> [[AND]]
658654
;
659655
%x.shift = ashr <4 x i8> %x, %shamt
@@ -665,10 +661,9 @@ define <4 x i8> @and_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %s
665661

666662
define <4 x i8> @and_ashr_not_vec_undef_1(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
667663
; CHECK-LABEL: @and_ashr_not_vec_undef_1(
668-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
669-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
670-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 undef, i8 undef, i8 undef>
671-
; CHECK-NEXT: [[AND:%.*]] = and <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
664+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
665+
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i8> [[TMP1]], [[X:%.*]]
666+
; CHECK-NEXT: [[AND:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
672667
; CHECK-NEXT: ret <4 x i8> [[AND]]
673668
;
674669
%x.shift = ashr <4 x i8> %x, %shamt
@@ -693,10 +688,9 @@ define <4 x i8> @and_ashr_not_vec_undef_2(<4 x i8> %x, <4 x i8> %y, <4 x i8> %sh
693688

694689
define i8 @or_ashr_not(i8 %x, i8 %y, i8 %shamt) {
695690
; CHECK-LABEL: @or_ashr_not(
696-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr i8 [[X:%.*]], [[SHAMT:%.*]]
697-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr i8 [[Y:%.*]], [[SHAMT]]
698-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor i8 [[Y_SHIFT]], -1
699-
; CHECK-NEXT: [[OR:%.*]] = or i8 [[X_SHIFT]], [[Y_SHIFT_NOT]]
691+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
692+
; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], [[X:%.*]]
693+
; CHECK-NEXT: [[OR:%.*]] = ashr i8 [[TMP2]], [[SHAMT:%.*]]
700694
; CHECK-NEXT: ret i8 [[OR]]
701695
;
702696
%x.shift = ashr i8 %x, %shamt
@@ -708,10 +702,9 @@ define i8 @or_ashr_not(i8 %x, i8 %y, i8 %shamt) {
708702

709703
define i8 @or_ashr_not_commuted(i8 %x, i8 %y, i8 %shamt) {
710704
; CHECK-LABEL: @or_ashr_not_commuted(
711-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr i8 [[X:%.*]], [[SHAMT:%.*]]
712-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr i8 [[Y:%.*]], [[SHAMT]]
713-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor i8 [[Y_SHIFT]], -1
714-
; CHECK-NEXT: [[OR:%.*]] = or i8 [[X_SHIFT]], [[Y_SHIFT_NOT]]
705+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
706+
; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], [[X:%.*]]
707+
; CHECK-NEXT: [[OR:%.*]] = ashr i8 [[TMP2]], [[SHAMT:%.*]]
715708
; CHECK-NEXT: ret i8 [[OR]]
716709
;
717710
%x.shift = ashr i8 %x, %shamt
@@ -774,10 +767,9 @@ define i8 @or_ashr_not_fail_invalid_xor_constant(i8 %x, i8 %y, i8 %shamt) {
774767

775768
define <4 x i8> @or_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
776769
; CHECK-LABEL: @or_ashr_not_vec(
777-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
778-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
779-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 -1, i8 -1, i8 -1>
780-
; CHECK-NEXT: [[OR:%.*]] = or <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
770+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
771+
; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i8> [[TMP1]], [[X:%.*]]
772+
; CHECK-NEXT: [[OR:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
781773
; CHECK-NEXT: ret <4 x i8> [[OR]]
782774
;
783775
%x.shift = ashr <4 x i8> %x, %shamt
@@ -789,10 +781,9 @@ define <4 x i8> @or_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
789781

790782
define <4 x i8> @or_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
791783
; CHECK-LABEL: @or_ashr_not_vec_commuted(
792-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
793-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
794-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 -1, i8 -1, i8 -1>
795-
; CHECK-NEXT: [[OR:%.*]] = or <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
784+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
785+
; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i8> [[TMP1]], [[X:%.*]]
786+
; CHECK-NEXT: [[OR:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
796787
; CHECK-NEXT: ret <4 x i8> [[OR]]
797788
;
798789
%x.shift = ashr <4 x i8> %x, %shamt
@@ -804,10 +795,9 @@ define <4 x i8> @or_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %sh
804795

805796
define <4 x i8> @or_ashr_not_vec_undef_1(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
806797
; CHECK-LABEL: @or_ashr_not_vec_undef_1(
807-
; CHECK-NEXT: [[X_SHIFT:%.*]] = ashr <4 x i8> [[X:%.*]], [[SHAMT:%.*]]
808-
; CHECK-NEXT: [[Y_SHIFT:%.*]] = ashr <4 x i8> [[Y:%.*]], [[SHAMT]]
809-
; CHECK-NEXT: [[Y_SHIFT_NOT:%.*]] = xor <4 x i8> [[Y_SHIFT]], <i8 -1, i8 undef, i8 undef, i8 undef>
810-
; CHECK-NEXT: [[OR:%.*]] = or <4 x i8> [[X_SHIFT]], [[Y_SHIFT_NOT]]
798+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
799+
; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i8> [[TMP1]], [[X:%.*]]
800+
; CHECK-NEXT: [[OR:%.*]] = ashr <4 x i8> [[TMP2]], [[SHAMT:%.*]]
811801
; CHECK-NEXT: ret <4 x i8> [[OR]]
812802
;
813803
%x.shift = ashr <4 x i8> %x, %shamt
@@ -832,9 +822,9 @@ define <4 x i8> @or_ashr_not_vec_undef_2(<4 x i8> %x, <4 x i8> %y, <4 x i8> %sha
832822

833823
define i8 @xor_ashr_not(i8 %x, i8 %y, i8 %shamt) {
834824
; CHECK-LABEL: @xor_ashr_not(
835-
; CHECK-NEXT: [[Y_SHIFT1:%.*]] = xor i8 [[Y:%.*]], [[X:%.*]]
836-
; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[Y_SHIFT1]], [[SHAMT:%.*]]
837-
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[TMP1]], -1
825+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], [[X:%.*]]
826+
; CHECK-NEXT: [[DOTNOT:%.*]] = ashr i8 [[TMP1]], [[SHAMT:%.*]]
827+
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[DOTNOT]], -1
838828
; CHECK-NEXT: ret i8 [[XOR]]
839829
;
840830
%x.shift = ashr i8 %x, %shamt
@@ -846,9 +836,9 @@ define i8 @xor_ashr_not(i8 %x, i8 %y, i8 %shamt) {
846836

847837
define i8 @xor_ashr_not_commuted(i8 %x, i8 %y, i8 %shamt) {
848838
; CHECK-LABEL: @xor_ashr_not_commuted(
849-
; CHECK-NEXT: [[Y_SHIFT1:%.*]] = xor i8 [[Y:%.*]], [[X:%.*]]
850-
; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[Y_SHIFT1]], [[SHAMT:%.*]]
851-
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[TMP1]], -1
839+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], [[X:%.*]]
840+
; CHECK-NEXT: [[DOTNOT:%.*]] = ashr i8 [[TMP1]], [[SHAMT:%.*]]
841+
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[DOTNOT]], -1
852842
; CHECK-NEXT: ret i8 [[XOR]]
853843
;
854844
%x.shift = ashr i8 %x, %shamt
@@ -910,9 +900,9 @@ define i8 @xor_ashr_not_fail_invalid_xor_constant(i8 %x, i8 %y, i8 %shamt) {
910900

911901
define <4 x i8> @xor_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
912902
; CHECK-LABEL: @xor_ashr_not_vec(
913-
; CHECK-NEXT: [[Y_SHIFT1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
914-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i8> [[Y_SHIFT1]], [[SHAMT:%.*]]
915-
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[TMP1]], <i8 -1, i8 -1, i8 -1, i8 -1>
903+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
904+
; CHECK-NEXT: [[DOTNOT:%.*]] = ashr <4 x i8> [[TMP1]], [[SHAMT:%.*]]
905+
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[DOTNOT]], <i8 -1, i8 -1, i8 -1, i8 -1>
916906
; CHECK-NEXT: ret <4 x i8> [[XOR]]
917907
;
918908
%x.shift = ashr <4 x i8> %x, %shamt
@@ -924,9 +914,9 @@ define <4 x i8> @xor_ashr_not_vec(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
924914

925915
define <4 x i8> @xor_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
926916
; CHECK-LABEL: @xor_ashr_not_vec_commuted(
927-
; CHECK-NEXT: [[Y_SHIFT1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
928-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i8> [[Y_SHIFT1]], [[SHAMT:%.*]]
929-
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[TMP1]], <i8 -1, i8 -1, i8 -1, i8 -1>
917+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
918+
; CHECK-NEXT: [[DOTNOT:%.*]] = ashr <4 x i8> [[TMP1]], [[SHAMT:%.*]]
919+
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[DOTNOT]], <i8 -1, i8 -1, i8 -1, i8 -1>
930920
; CHECK-NEXT: ret <4 x i8> [[XOR]]
931921
;
932922
%x.shift = ashr <4 x i8> %x, %shamt
@@ -938,9 +928,9 @@ define <4 x i8> @xor_ashr_not_vec_commuted(<4 x i8> %x, <4 x i8> %y, <4 x i8> %s
938928

939929
define <4 x i8> @xor_ashr_not_vec_undef_1(<4 x i8> %x, <4 x i8> %y, <4 x i8> %shamt) {
940930
; CHECK-LABEL: @xor_ashr_not_vec_undef_1(
941-
; CHECK-NEXT: [[Y_SHIFT1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
942-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i8> [[Y_SHIFT1]], [[SHAMT:%.*]]
943-
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[TMP1]], <i8 -1, i8 undef, i8 undef, i8 undef>
931+
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i8> [[Y:%.*]], [[X:%.*]]
932+
; CHECK-NEXT: [[DOTNOT:%.*]] = ashr <4 x i8> [[TMP1]], [[SHAMT:%.*]]
933+
; CHECK-NEXT: [[XOR:%.*]] = xor <4 x i8> [[DOTNOT]], <i8 -1, i8 -1, i8 -1, i8 -1>
944934
; CHECK-NEXT: ret <4 x i8> [[XOR]]
945935
;
946936
%x.shift = ashr <4 x i8> %x, %shamt

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