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[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC
Rather than using operator[] on getFeatureBits we can use hasFeature to shorten the code. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D144300
1 parent d9e4c10 commit 34aff47

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5 files changed

+29
-37
lines changed

5 files changed

+29
-37
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -183,19 +183,15 @@ class RISCVAsmParser : public MCTargetAsmParser {
183183
bool parseDirectiveVariantCC();
184184

185185
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
186-
if (!(getSTI().getFeatureBits()[Feature])) {
186+
if (!(getSTI().hasFeature(Feature))) {
187187
MCSubtargetInfo &STI = copySTI();
188188
setAvailableFeatures(
189189
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
190190
}
191191
}
192192

193-
bool getFeatureBits(uint64_t Feature) {
194-
return getSTI().getFeatureBits()[Feature];
195-
}
196-
197193
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
198-
if (getSTI().getFeatureBits()[Feature]) {
194+
if (getSTI().hasFeature(Feature)) {
199195
MCSubtargetInfo &STI = copySTI();
200196
setAvailableFeatures(
201197
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
@@ -249,13 +245,12 @@ class RISCVAsmParser : public MCTargetAsmParser {
249245
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
250246

251247
auto ABIName = StringRef(Options.ABIName);
252-
if (ABIName.endswith("f") &&
253-
!getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) {
248+
if (ABIName.endswith("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
254249
errs() << "Hard-float 'f' ABI can't be used for a target that "
255250
"doesn't support the F instruction set extension (ignoring "
256251
"target-abi)\n";
257252
} else if (ABIName.endswith("d") &&
258-
!getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {
253+
!getSTI().hasFeature(RISCV::FeatureStdExtD)) {
259254
errs() << "Hard-float 'd' ABI can't be used for a target that "
260255
"doesn't support the D instruction set extension (ignoring "
261256
"target-abi)\n";
@@ -2045,7 +2040,7 @@ bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info,
20452040
// cause relaxations. Unfortunately instruction processing stage occurs in the
20462041
// same pass as relocation emission, so it's too late to set a 'sticky bit'
20472042
// for the entire file.
2048-
if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) {
2043+
if (getSTI().hasFeature(RISCV::FeatureRelax)) {
20492044
auto *Assembler = getTargetStreamer().getStreamer().getAssemblerPtr();
20502045
if (Assembler != nullptr) {
20512046
RISCVAsmBackend &MAB =

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
6161
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
6262
uint64_t Address,
6363
const MCDisassembler *Decoder) {
64-
const FeatureBitset &FeatureBits =
65-
Decoder->getSubtargetInfo().getFeatureBits();
66-
bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
64+
bool IsRV32E = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRV32E);
6765

6866
if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
6967
return MCDisassembler::Fail;
@@ -448,58 +446,58 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
448446

449447
Insn = support::endian::read32le(Bytes.data());
450448

451-
if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
452-
!STI.getFeatureBits()[RISCV::Feature64Bit]) {
449+
if (STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
450+
!STI.hasFeature(RISCV::Feature64Bit)) {
453451
LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
454452
"rv32)\n");
455453
Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
456454
this, STI);
457455
if (Result != MCDisassembler::Fail)
458456
return Result;
459457
}
460-
if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
458+
if (STI.hasFeature(RISCV::FeatureStdExtZfinx)) {
461459
LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
462460
Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
463461
STI);
464462
if (Result != MCDisassembler::Fail)
465463
return Result;
466464
}
467-
if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) {
465+
if (STI.hasFeature(RISCV::FeatureVendorXVentanaCondOps)) {
468466
LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
469467
Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
470468
STI);
471469
if (Result != MCDisassembler::Fail)
472470
return Result;
473471
}
474-
if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBa]) {
472+
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBa)) {
475473
LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n");
476474
Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this,
477475
STI);
478476
if (Result != MCDisassembler::Fail)
479477
return Result;
480478
}
481-
if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBb]) {
479+
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBb)) {
482480
LLVM_DEBUG(dbgs() << "Trying XTHeadBb custom opcode table:\n");
483481
Result = decodeInstruction(DecoderTableTHeadBb32, MI, Insn, Address, this,
484482
STI);
485483
if (Result != MCDisassembler::Fail)
486484
return Result;
487485
}
488-
if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBs]) {
486+
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) {
489487
LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n");
490488
Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this,
491489
STI);
492490
if (Result != MCDisassembler::Fail)
493491
return Result;
494492
}
495-
if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadMac]) {
493+
if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) {
496494
LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n");
497495
Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address,
498496
this, STI);
499497
if (Result != MCDisassembler::Fail)
500498
return Result;
501499
}
502-
if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
500+
if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) {
503501
LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
504502
Result =
505503
decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
@@ -519,7 +517,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
519517

520518
Insn = support::endian::read16le(Bytes.data());
521519

522-
if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
520+
if (!STI.hasFeature(RISCV::Feature64Bit)) {
523521
LLVM_DEBUG(
524522
dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
525523
// Calling the auto-generated decoder function.

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
134134
return true;
135135
}
136136

137-
return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
137+
return STI.hasFeature(RISCV::FeatureRelax) || ForceRelocs;
138138
}
139139

140140
bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
@@ -374,11 +374,11 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
374374
Count -= 1;
375375
}
376376

377-
bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
378-
bool HasStdExtZca = STI->getFeatureBits()[RISCV::FeatureExtZca];
377+
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
378+
STI->hasFeature(RISCV::FeatureExtZca);
379379
// The canonical nop on RVC is c.nop.
380380
if (Count % 4 == 2) {
381-
OS.write((HasStdExtC || HasStdExtZca) ? "\x01\0" : "\0\0", 2);
381+
OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2);
382382
Count -= 2;
383383
}
384384

@@ -602,11 +602,11 @@ bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
602602
const MCAlignFragment &AF, unsigned &Size) {
603603
// Calculate Nops Size only when linker relaxation enabled.
604604
const MCSubtargetInfo *STI = AF.getSubtargetInfo();
605-
if (!STI->getFeatureBits()[RISCV::FeatureRelax])
605+
if (!STI->hasFeature(RISCV::FeatureRelax))
606606
return false;
607607

608-
bool UseCompressedNop = STI->getFeatureBits()[RISCV::FeatureStdExtC] ||
609-
STI->getFeatureBits()[RISCV::FeatureExtZca];
608+
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
609+
STI->hasFeature(RISCV::FeatureExtZca);
610610
unsigned MinNopLen = UseCompressedNop ? 2 : 4;
611611

612612
if (AF.getAlignment() <= MinNopLen) {
@@ -627,7 +627,7 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
627627
MCAlignFragment &AF) {
628628
// Insert the fixup only when linker relaxation enabled.
629629
const MCSubtargetInfo *STI = AF.getSubtargetInfo();
630-
if (!STI->getFeatureBits()[RISCV::FeatureRelax])
630+
if (!STI->hasFeature(RISCV::FeatureRelax))
631631
return false;
632632

633633
// Calculate total Nops we need to insert. If there are none to insert

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
168168
0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
169169

170170
// Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
171-
if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
171+
if (STI.hasFeature(RISCV::FeatureRelax)) {
172172
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
173173
Fixups.push_back(MCFixup::create(
174174
0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
@@ -215,8 +215,8 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
215215
Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
216216

217217
bool UseCompressedBr = false;
218-
if (IsEqTest && (STI.getFeatureBits()[RISCV::FeatureStdExtC] ||
219-
STI.getFeatureBits()[RISCV::FeatureExtZca])) {
218+
if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) ||
219+
STI.hasFeature(RISCV::FeatureExtZca))) {
220220
if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
221221
SrcReg2.id() == RISCV::X0) {
222222
UseCompressedBr = true;
@@ -344,7 +344,7 @@ RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
344344
unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
345345
SmallVectorImpl<MCFixup> &Fixups,
346346
const MCSubtargetInfo &STI) const {
347-
bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
347+
bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax);
348348
const MCOperand &MO = MI.getOperand(OpNo);
349349

350350
MCInstrDesc const &Desc = MCII.get(MI.getOpcode());

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12704,8 +12704,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
1270412704
case CallingConv::Fast:
1270512705
break;
1270612706
case CallingConv::GHC:
12707-
if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] ||
12708-
!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD])
12707+
if (!Subtarget.hasStdExtF() || !Subtarget.hasStdExtD())
1270912708
report_fatal_error(
1271012709
"GHC calling convention requires the F and D instruction set extensions");
1271112710
}

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