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Merge commit '45968da95d89' from llvm.org/main into next
2 parents f726f66 + 45968da commit 363b3d8

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3 files changed

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‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12074,11 +12074,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
1207412074
return std::nullopt;
1207512075
auto VecIdx = IdxOp->getZExtValue();
1207612076
auto ScalarSize = Op.getScalarValueSizeInBits();
12077-
if (ScalarSize != 32) {
12077+
if (ScalarSize < 32)
1207812078
Index = ScalarSize == 8 ? VecIdx : VecIdx * 2 + Index;
12079-
}
12080-
12081-
return calculateSrcByte(ScalarSize == 32 ? Op : Op.getOperand(0),
12079+
return calculateSrcByte(ScalarSize >= 32 ? Op : Op.getOperand(0),
1208212080
StartingIndex, Index);
1208312081
}
1208412082

‎llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,109 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GFX9 %s
3+
; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 %s -o - | FileCheck -check-prefix=GFX10 %s
4+
; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 %s -o - | FileCheck -check-prefix=GFX11 %s
5+
6+
define amdgpu_kernel void @test(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
7+
; GFX9-LABEL: test:
8+
; GFX9: ; %bb.0: ; %entry
9+
; GFX9-NEXT: s_load_dword s7, s[4:5], 0x1c
10+
; GFX9-NEXT: s_load_dword s8, s[4:5], 0x38
11+
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
12+
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
13+
; GFX9-NEXT: s_and_b32 s4, s7, 0xffff
14+
; GFX9-NEXT: s_mul_i32 s6, s6, s4
15+
; GFX9-NEXT: s_add_i32 s8, s8, s6
16+
; GFX9-NEXT: v_add_u32_e32 v0, s8, v0
17+
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
18+
; GFX9-NEXT: v_lshlrev_b64 v[4:5], 4, v[0:1]
19+
; GFX9-NEXT: v_mov_b32_e32 v1, s1
20+
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v4
21+
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v5, vcc
22+
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
23+
; GFX9-NEXT: v_mov_b32_e32 v6, s3
24+
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s2, v4
25+
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
26+
; GFX9-NEXT: s_waitcnt vmcnt(0)
27+
; GFX9-NEXT: v_not_b32_e32 v3, v3
28+
; GFX9-NEXT: v_not_b32_e32 v2, v2
29+
; GFX9-NEXT: v_not_b32_e32 v1, v1
30+
; GFX9-NEXT: v_not_b32_e32 v0, v0
31+
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
32+
; GFX9-NEXT: s_endpgm
33+
;
34+
; GFX10-LABEL: test:
35+
; GFX10: ; %bb.0: ; %entry
36+
; GFX10-NEXT: s_clause 0x2
37+
; GFX10-NEXT: s_load_dword s7, s[4:5], 0x1c
38+
; GFX10-NEXT: s_load_dword s8, s[4:5], 0x38
39+
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
40+
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
41+
; GFX10-NEXT: s_and_b32 s4, s7, 0xffff
42+
; GFX10-NEXT: s_mul_i32 s6, s6, s4
43+
; GFX10-NEXT: v_add3_u32 v0, s8, s6, v0
44+
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0
45+
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 4, v[0:1]
46+
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v4
47+
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
48+
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, s2, v4
49+
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
50+
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
51+
; GFX10-NEXT: s_waitcnt vmcnt(0)
52+
; GFX10-NEXT: v_not_b32_e32 v3, v3
53+
; GFX10-NEXT: v_not_b32_e32 v2, v2
54+
; GFX10-NEXT: v_not_b32_e32 v1, v1
55+
; GFX10-NEXT: v_not_b32_e32 v0, v0
56+
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
57+
; GFX10-NEXT: s_endpgm
58+
;
59+
; GFX11-LABEL: test:
60+
; GFX11: ; %bb.0: ; %entry
61+
; GFX11-NEXT: s_clause 0x2
62+
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x1c
63+
; GFX11-NEXT: s_load_b32 s5, s[0:1], 0x38
64+
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
65+
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
66+
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
67+
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
68+
; GFX11-NEXT: s_mul_i32 s15, s15, s4
69+
; GFX11-NEXT: v_add3_u32 v0, s5, s15, v0
70+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
71+
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
72+
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 4, v[0:1]
73+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
74+
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, s0, v4
75+
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
76+
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, s2, v4
77+
; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
78+
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
79+
; GFX11-NEXT: s_waitcnt vmcnt(0)
80+
; GFX11-NEXT: v_not_b32_e32 v3, v3
81+
; GFX11-NEXT: v_not_b32_e32 v2, v2
82+
; GFX11-NEXT: v_not_b32_e32 v1, v1
83+
; GFX11-NEXT: v_not_b32_e32 v0, v0
84+
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
85+
; GFX11-NEXT: s_nop 0
86+
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
87+
; GFX11-NEXT: s_endpgm
88+
entry:
89+
%implicitarg.ptr = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
90+
%arg.1.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 40
91+
%arg.1 = load i64, ptr addrspace(4) %arg.1.ptr, align 8
92+
%workgroup.id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
93+
%arg.2.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 12
94+
%arg.2 = load i16, ptr addrspace(4) %arg.2.ptr, align 4
95+
%arg.2.ext = zext i16 %arg.2 to i32
96+
%mul = mul i32 %workgroup.id.x, %arg.2.ext
97+
%workitem.id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
98+
%add = add i32 %mul, %workitem.id.x
99+
%add.ext = zext i32 %add to i64
100+
%add.1 = add i64 %arg.1, %add.ext
101+
%sext = shl i64 %add.1, 32
102+
%idxprom = ashr exact i64 %sext, 32
103+
%arrayidx = getelementptr inbounds <16 x i8>, ptr addrspace(1) %src, i64 %idxprom
104+
%arrayval = load <16 x i8>, ptr addrspace(1) %arrayidx, align 16
105+
%not = xor <16 x i8> %arrayval, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
106+
%arrayidx2 = getelementptr inbounds <16 x i8>, ptr addrspace(1) %dst, i64 %idxprom
107+
store <16 x i8> %not, ptr addrspace(1) %arrayidx2, align 16
108+
ret void
109+
}

‎llvm/test/CodeGen/AMDGPU/permute_i8.ll

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3816,28 +3816,31 @@ define hidden void @extract_v13i64(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
38163816
; GFX10-LABEL: extract_v13i64:
38173817
; GFX10: ; %bb.0:
38183818
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3819-
; GFX10-NEXT: s_clause 0x1
3820-
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off
3821-
; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16
3819+
; GFX10-NEXT: s_clause 0x2
3820+
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:48
3821+
; GFX10-NEXT: global_load_dwordx4 v[11:14], v[0:1], off
3822+
; GFX10-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:64
3823+
; GFX10-NEXT: ; kill: killed $vgpr0 killed $vgpr1
38223824
; GFX10-NEXT: s_waitcnt vmcnt(1)
3823-
; GFX10-NEXT: v_perm_b32 v0, v9, v8, 0x3020504
3825+
; GFX10-NEXT: v_perm_b32 v0, v12, v13, 0x1000504
38243826
; GFX10-NEXT: s_waitcnt vmcnt(0)
3825-
; GFX10-NEXT: v_perm_b32 v1, v11, v12, 0x1000706
3827+
; GFX10-NEXT: v_perm_b32 v1, v10, v14, 0x1000504
38263828
; GFX10-NEXT: global_store_dword v[4:5], v0, off
38273829
; GFX10-NEXT: global_store_dword v[6:7], v1, off
38283830
; GFX10-NEXT: s_setpc_b64 s[30:31]
38293831
;
38303832
; GFX9-LABEL: extract_v13i64:
38313833
; GFX9: ; %bb.0:
38323834
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3833-
; GFX9-NEXT: global_load_dwordx4 v[8:11], v[0:1], off
3834-
; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16
3835-
; GFX9-NEXT: s_mov_b32 s4, 0x3020504
3836-
; GFX9-NEXT: s_mov_b32 s5, 0x1000706
3835+
; GFX9-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:48
3836+
; GFX9-NEXT: global_load_dwordx4 v[11:14], v[0:1], off
3837+
; GFX9-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:64
3838+
; GFX9-NEXT: s_mov_b32 s4, 0x1000504
3839+
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
38373840
; GFX9-NEXT: s_waitcnt vmcnt(1)
3838-
; GFX9-NEXT: v_perm_b32 v0, v9, v8, s4
3841+
; GFX9-NEXT: v_perm_b32 v0, v12, v13, s4
38393842
; GFX9-NEXT: s_waitcnt vmcnt(0)
3840-
; GFX9-NEXT: v_perm_b32 v1, v11, v12, s5
3843+
; GFX9-NEXT: v_perm_b32 v1, v10, v14, s4
38413844
; GFX9-NEXT: global_store_dword v[4:5], v0, off
38423845
; GFX9-NEXT: global_store_dword v[6:7], v1, off
38433846
; GFX9-NEXT: s_waitcnt vmcnt(0)

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