@@ -3606,25 +3606,18 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
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Tmp = VTBits - SrcVT.getScalarSizeInBits ();
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return ComputeNumSignBits (Src, DemandedSrcElts, Depth+1 ) + Tmp;
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}
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-
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case ISD::SRA:
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- Tmp = ComputeNumSignBits (Op.getOperand (0 ), DemandedElts, Depth+ 1 );
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+ Tmp = ComputeNumSignBits (Op.getOperand (0 ), DemandedElts, Depth + 1 );
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// SRA X, C -> adds C sign bits.
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- if (ConstantSDNode *C =
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- isConstOrConstSplat (Op.getOperand (1 ), DemandedElts)) {
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- APInt ShiftVal = C->getAPIntValue ();
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- ShiftVal += Tmp;
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- Tmp = ShiftVal.uge (VTBits) ? VTBits : ShiftVal.getZExtValue ();
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- }
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+ if (const APInt *ShAmt = getValidShiftAmountConstant (Op, DemandedElts))
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+ Tmp = std::min<uint64_t >(Tmp + ShAmt->getZExtValue (), VTBits);
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return Tmp;
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case ISD::SHL:
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- if (ConstantSDNode *C =
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- isConstOrConstSplat (Op.getOperand (1 ), DemandedElts)) {
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- // shl destroys sign bits.
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- Tmp = ComputeNumSignBits (Op.getOperand (0 ), DemandedElts, Depth+1 );
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- if (C->getAPIntValue ().uge (VTBits) || // Bad shift.
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- C->getAPIntValue ().uge (Tmp)) break ; // Shifted all sign bits out.
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- return Tmp - C->getZExtValue ();
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+ if (const APInt *ShAmt = getValidShiftAmountConstant (Op, DemandedElts)) {
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+ // shl destroys sign bits, ensure it doesn't shift out all sign bits.
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+ Tmp = ComputeNumSignBits (Op.getOperand (0 ), DemandedElts, Depth + 1 );
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+ if (ShAmt->ult (Tmp))
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+ return Tmp - ShAmt->getZExtValue ();
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}
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break ;
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case ISD::AND:
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