Skip to content

Commit 3a76de4

Browse files
author
Muhammad Asif Manzoor
committed
[AArch64][SVE] Add lowering for llvm frecpx
Add the functionality to lower frecpx for passthru variant Reviewed By: paulwalker-arm Differential Revision: https://reviews.llvm.org/D88032
1 parent f161e84 commit 3a76de4

File tree

4 files changed

+23
-21
lines changed

4 files changed

+23
-21
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ static bool isMergePassthruOpcode(unsigned Opc) {
171171
case AArch64ISD::FCVTZU_MERGE_PASSTHRU:
172172
case AArch64ISD::FCVTZS_MERGE_PASSTHRU:
173173
case AArch64ISD::FSQRT_MERGE_PASSTHRU:
174+
case AArch64ISD::FRECPX_MERGE_PASSTHRU:
174175
return true;
175176
}
176177
}
@@ -1555,6 +1556,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
15551556
MAKE_CASE(AArch64ISD::FCVTZU_MERGE_PASSTHRU)
15561557
MAKE_CASE(AArch64ISD::FCVTZS_MERGE_PASSTHRU)
15571558
MAKE_CASE(AArch64ISD::FSQRT_MERGE_PASSTHRU)
1559+
MAKE_CASE(AArch64ISD::FRECPX_MERGE_PASSTHRU)
15581560
MAKE_CASE(AArch64ISD::SETCC_MERGE_ZERO)
15591561
MAKE_CASE(AArch64ISD::ADC)
15601562
MAKE_CASE(AArch64ISD::SBC)
@@ -3475,6 +3477,9 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
34753477
case Intrinsic::aarch64_sve_fsqrt:
34763478
return DAG.getNode(AArch64ISD::FSQRT_MERGE_PASSTHRU, dl, Op.getValueType(),
34773479
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3480+
case Intrinsic::aarch64_sve_frecpx:
3481+
return DAG.getNode(AArch64ISD::FRECPX_MERGE_PASSTHRU, dl, Op.getValueType(),
3482+
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
34783483
case Intrinsic::aarch64_sve_convert_to_svbool: {
34793484
EVT OutVT = Op.getValueType();
34803485
EVT InVT = Op.getOperand(1).getValueType();

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@ enum NodeType : unsigned {
9999
FFLOOR_MERGE_PASSTHRU,
100100
FNEARBYINT_MERGE_PASSTHRU,
101101
FNEG_MERGE_PASSTHRU,
102+
FRECPX_MERGE_PASSTHRU,
102103
FRINT_MERGE_PASSTHRU,
103104
FROUND_MERGE_PASSTHRU,
104105
FROUNDEVEN_MERGE_PASSTHRU,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,7 @@ def AArch64frinta_mt : SDNode<"AArch64ISD::FROUND_MERGE_PASSTHRU", SDT_AArch64Ar
212212
def AArch64frintn_mt : SDNode<"AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU", SDT_AArch64Arith>;
213213
def AArch64frintz_mt : SDNode<"AArch64ISD::FTRUNC_MERGE_PASSTHRU", SDT_AArch64Arith>;
214214
def AArch64fsqrt_mt : SDNode<"AArch64ISD::FSQRT_MERGE_PASSTHRU", SDT_AArch64Arith>;
215+
def AArch64frecpx_mt : SDNode<"AArch64ISD::FRECPX_MERGE_PASSTHRU", SDT_AArch64Arith>;
215216

216217
def SDT_AArch64FCVT : SDTypeProfile<1, 3, [
217218
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
@@ -1473,15 +1474,15 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
14731474
(nxv2i64 (AArch64dup (i64 0xFFFFFFFF)))), (nxv2f64 ZPR:$Zd))),
14741475
(UCVTF_ZPmZ_StoD ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>;
14751476

1476-
defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", null_frag, AArch64frintn_mt>;
1477-
defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp", null_frag, AArch64frintp_mt>;
1478-
defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm", null_frag, AArch64frintm_mt>;
1479-
defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz", null_frag, AArch64frintz_mt>;
1480-
defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta", null_frag, AArch64frinta_mt>;
1481-
defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx", null_frag, AArch64frintx_mt>;
1482-
defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti", null_frag, AArch64frinti_mt>;
1483-
defm FRECPX_ZPmZ : sve_fp_2op_p_zd_HSD<0b01100, "frecpx", int_aarch64_sve_frecpx>;
1484-
defm FSQRT_ZPmZ : sve_fp_2op_p_zd_HSD<0b01101, "fsqrt", null_frag, AArch64fsqrt_mt>;
1477+
defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", AArch64frintn_mt>;
1478+
defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp", AArch64frintp_mt>;
1479+
defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm", AArch64frintm_mt>;
1480+
defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz", AArch64frintz_mt>;
1481+
defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta", AArch64frinta_mt>;
1482+
defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx", AArch64frintx_mt>;
1483+
defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti", AArch64frinti_mt>;
1484+
defm FRECPX_ZPmZ : sve_fp_2op_p_zd_HSD<0b01100, "frecpx", AArch64frecpx_mt>;
1485+
defm FSQRT_ZPmZ : sve_fp_2op_p_zd_HSD<0b01101, "fsqrt", AArch64fsqrt_mt>;
14851486

14861487
let Predicates = [HasBF16, HasSVE] in {
14871488
defm BFDOT_ZZZ : sve_bfloat_dot<"bfdot", int_aarch64_sve_bfdot>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2299,22 +2299,17 @@ multiclass sve_fp_2op_p_zd<bits<7> opc, string asm,
22992299
def : SVE_1_Op_Passthru_Pat<vt1, ir_op, vt2, vt3, !cast<Instruction>(NAME)>;
23002300
}
23012301

2302-
multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm, SDPatternOperator op_merge,
2303-
SDPatternOperator op_pt = null_frag> {
2302+
multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm, SDPatternOperator op> {
23042303
def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>;
23052304
def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>;
23062305
def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
23072306

2308-
def : SVE_3_Op_Pat<nxv8f16, op_merge, nxv8f16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2309-
def : SVE_3_Op_Pat<nxv4f32, op_merge, nxv4f32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2310-
def : SVE_3_Op_Pat<nxv2f64, op_merge, nxv2f64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
2311-
2312-
def : SVE_1_Op_Passthru_Pat<nxv8f16, op_pt, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2313-
def : SVE_1_Op_Passthru_Pat<nxv4f16, op_pt, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
2314-
def : SVE_1_Op_Passthru_Pat<nxv2f16, op_pt, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
2315-
def : SVE_1_Op_Passthru_Pat<nxv4f32, op_pt, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2316-
def : SVE_1_Op_Passthru_Pat<nxv2f32, op_pt, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
2317-
def : SVE_1_Op_Passthru_Pat<nxv2f64, op_pt, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
2307+
def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2308+
def : SVE_1_Op_Passthru_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
2309+
def : SVE_1_Op_Passthru_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
2310+
def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2311+
def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
2312+
def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
23182313
}
23192314

23202315
multiclass sve2_fp_flogb<string asm, SDPatternOperator op> {

0 commit comments

Comments
 (0)