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[InstCombine] add tests for shift-logic-shift; NFC
This is based on existing CodeGen test files for x86 and AArch64. The corresponding potential transform is shown in: rL370617
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‎llvm/test/Transforms/InstCombine/shift-logic.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i8 @shl_and(i8 %x, i8 %y) {
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; CHECK-LABEL: @shl_and(
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; CHECK-NEXT: [[SH0:%.*]] = shl i8 [[X:%.*]], 3
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; CHECK-NEXT: [[R:%.*]] = and i8 [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = shl i8 [[R]], 2
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; CHECK-NEXT: ret i8 [[SH1]]
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;
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%sh0 = shl i8 %x, 3
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%r = and i8 %sh0, %y
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%sh1 = shl i8 %r, 2
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ret i8 %sh1
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}
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define i16 @shl_or(i16 %x, i16 %py) {
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; CHECK-LABEL: @shl_or(
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; CHECK-NEXT: [[Y:%.*]] = srem i16 [[PY:%.*]], 42
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; CHECK-NEXT: [[SH0:%.*]] = shl i16 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = or i16 [[Y]], [[SH0]]
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; CHECK-NEXT: [[SH1:%.*]] = shl i16 [[R]], 7
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; CHECK-NEXT: ret i16 [[SH1]]
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;
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%y = srem i16 %py, 42 ; thwart complexity-based canonicalization
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%sh0 = shl i16 %x, 5
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%r = or i16 %y, %sh0
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%sh1 = shl i16 %r, 7
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ret i16 %sh1
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}
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define i32 @shl_xor(i32 %x, i32 %y) {
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; CHECK-LABEL: @shl_xor(
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; CHECK-NEXT: [[SH0:%.*]] = shl i32 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 [[R]], 7
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; CHECK-NEXT: ret i32 [[SH1]]
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;
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%sh0 = shl i32 %x, 5
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%r = xor i32 %sh0, %y
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%sh1 = shl i32 %r, 7
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ret i32 %sh1
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}
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define i64 @lshr_and(i64 %x, i64 %py) {
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; CHECK-LABEL: @lshr_and(
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; CHECK-NEXT: [[Y:%.*]] = srem i64 [[PY:%.*]], 42
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; CHECK-NEXT: [[SH0:%.*]] = lshr i64 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = and i64 [[Y]], [[SH0]]
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; CHECK-NEXT: [[SH1:%.*]] = lshr i64 [[R]], 7
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; CHECK-NEXT: ret i64 [[SH1]]
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;
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%y = srem i64 %py, 42 ; thwart complexity-based canonicalization
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%sh0 = lshr i64 %x, 5
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%r = and i64 %y, %sh0
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%sh1 = lshr i64 %r, 7
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ret i64 %sh1
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}
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define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @lshr_or(
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; CHECK-NEXT: [[SH0:%.*]] = lshr <4 x i32> [[X:%.*]], <i32 5, i32 5, i32 5, i32 5>
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; CHECK-NEXT: [[R:%.*]] = or <4 x i32> [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = lshr <4 x i32> [[R]], <i32 7, i32 7, i32 7, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[SH1]]
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;
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%sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = or <4 x i32> %sh0, %y
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%sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %sh1
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}
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define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %py) {
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; CHECK-LABEL: @lshr_xor(
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; CHECK-NEXT: [[Y:%.*]] = srem <8 x i16> [[PY:%.*]], <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
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; CHECK-NEXT: [[SH0:%.*]] = lshr <8 x i16> [[X:%.*]], <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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; CHECK-NEXT: [[R:%.*]] = xor <8 x i16> [[Y]], [[SH0]]
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; CHECK-NEXT: [[SH1:%.*]] = lshr <8 x i16> [[R]], <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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; CHECK-NEXT: ret <8 x i16> [[SH1]]
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;
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%y = srem <8 x i16> %py, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 -42> ; thwart complexity-based canonicalization
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%sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = xor <8 x i16> %y, %sh0
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%sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %sh1
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}
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define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %py, <16 x i8> %pz) {
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; CHECK-LABEL: @ashr_and(
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; CHECK-NEXT: [[Y:%.*]] = srem <16 x i8> [[PY:%.*]], [[PZ:%.*]]
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; CHECK-NEXT: [[SH0:%.*]] = ashr <16 x i8> [[X:%.*]], <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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; CHECK-NEXT: [[R:%.*]] = and <16 x i8> [[Y]], [[SH0]]
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; CHECK-NEXT: [[SH1:%.*]] = ashr <16 x i8> [[R]], <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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; CHECK-NEXT: ret <16 x i8> [[SH1]]
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;
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%y = srem <16 x i8> %py, %pz ; thwart complexity-based canonicalization
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%sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%r = and <16 x i8> %y, %sh0
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%sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <16 x i8> %sh1
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}
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define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: @ashr_or(
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; CHECK-NEXT: [[SH0:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 5, i64 5>
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; CHECK-NEXT: [[R:%.*]] = or <2 x i64> [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = ashr <2 x i64> [[R]], <i64 7, i64 7>
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; CHECK-NEXT: ret <2 x i64> [[SH1]]
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;
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%sh0 = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = or <2 x i64> %sh0, %y
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%sh1 = ashr <2 x i64> %r, <i64 7, i64 7>
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ret <2 x i64> %sh1
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}
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define i32 @ashr_xor(i32 %x, i32 %py) {
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; CHECK-LABEL: @ashr_xor(
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; CHECK-NEXT: [[Y:%.*]] = srem i32 [[PY:%.*]], 42
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; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[Y]], [[SH0]]
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; CHECK-NEXT: [[SH1:%.*]] = ashr i32 [[R]], 7
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; CHECK-NEXT: ret i32 [[SH1]]
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;
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%y = srem i32 %py, 42 ; thwart complexity-based canonicalization
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @shr_mismatch_xor(i32 %x, i32 %y) {
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; CHECK-LABEL: @shr_mismatch_xor(
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; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = lshr i32 [[R]], 7
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; CHECK-NEXT: ret i32 [[SH1]]
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;
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @ashr_overshift_xor(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_overshift_xor(
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; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 15
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = ashr i32 [[R]], 17
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; CHECK-NEXT: ret i32 [[SH1]]
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;
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%sh0 = ashr i32 %x, 15
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 17
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ret i32 %sh1
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}
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define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @lshr_or_extra_use(
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; CHECK-NEXT: [[SH0:%.*]] = lshr i32 [[X:%.*]], 5
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; CHECK-NEXT: [[R:%.*]] = or i32 [[SH0]], [[Y:%.*]]
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; CHECK-NEXT: store i32 [[R]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[SH1:%.*]] = lshr i32 [[R]], 7
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; CHECK-NEXT: ret i32 [[SH1]]
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;
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%sh0 = lshr i32 %x, 5
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%r = or i32 %sh0, %y
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store i32 %r, i32* %p
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}

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