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[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
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lines changed

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
8080
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
8181
return &TSInfo;
8282
}
83+
bool enableMachineScheduler() const override { return true; }
8384
bool hasStdExtM() const { return HasStdExtM; }
8485
bool hasStdExtA() const { return HasStdExtA; }
8586
bool hasStdExtF() const { return HasStdExtF; }

‎llvm/test/CodeGen/RISCV/add-before-shl.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -96,36 +96,36 @@ define i128 @add_wide_operand(i128 %a) nounwind {
9696
; RV32I-LABEL: add_wide_operand:
9797
; RV32I: # %bb.0:
9898
; RV32I-NEXT: lw a2, 0(a1)
99-
; RV32I-NEXT: srli a3, a2, 29
100-
; RV32I-NEXT: lw a4, 4(a1)
101-
; RV32I-NEXT: slli a5, a4, 3
102-
; RV32I-NEXT: or a6, a5, a3
103-
; RV32I-NEXT: srli a4, a4, 29
104-
; RV32I-NEXT: lw a5, 8(a1)
105-
; RV32I-NEXT: slli a3, a5, 3
106-
; RV32I-NEXT: or a3, a3, a4
99+
; RV32I-NEXT: lw a3, 4(a1)
100+
; RV32I-NEXT: lw a6, 12(a1)
101+
; RV32I-NEXT: lw a1, 8(a1)
102+
; RV32I-NEXT: srli a5, a2, 29
103+
; RV32I-NEXT: slli a4, a3, 3
104+
; RV32I-NEXT: or a4, a4, a5
105+
; RV32I-NEXT: srli a3, a3, 29
106+
; RV32I-NEXT: slli a5, a1, 3
107+
; RV32I-NEXT: or a3, a5, a3
108+
; RV32I-NEXT: srli a1, a1, 29
109+
; RV32I-NEXT: slli a5, a6, 3
110+
; RV32I-NEXT: or a1, a5, a1
107111
; RV32I-NEXT: slli a2, a2, 3
112+
; RV32I-NEXT: lui a5, 128
113+
; RV32I-NEXT: add a1, a1, a5
108114
; RV32I-NEXT: sw a2, 0(a0)
109115
; RV32I-NEXT: sw a3, 8(a0)
110-
; RV32I-NEXT: sw a6, 4(a0)
111-
; RV32I-NEXT: srli a2, a5, 29
112-
; RV32I-NEXT: lw a1, 12(a1)
113-
; RV32I-NEXT: slli a1, a1, 3
114-
; RV32I-NEXT: or a1, a1, a2
115-
; RV32I-NEXT: lui a2, 128
116-
; RV32I-NEXT: add a1, a1, a2
116+
; RV32I-NEXT: sw a4, 4(a0)
117117
; RV32I-NEXT: sw a1, 12(a0)
118118
; RV32I-NEXT: ret
119119
;
120120
; RV64I-LABEL: add_wide_operand:
121121
; RV64I: # %bb.0:
122-
; RV64I-NEXT: slli a1, a1, 3
123122
; RV64I-NEXT: srli a2, a0, 61
123+
; RV64I-NEXT: slli a1, a1, 3
124124
; RV64I-NEXT: or a1, a1, a2
125+
; RV64I-NEXT: slli a0, a0, 3
125126
; RV64I-NEXT: addi a2, zero, 1
126127
; RV64I-NEXT: slli a2, a2, 51
127128
; RV64I-NEXT: add a1, a1, a2
128-
; RV64I-NEXT: slli a0, a0, 3
129129
; RV64I-NEXT: ret
130130
%1 = add i128 %a, 5192296858534827628530496329220096
131131
%2 = shl i128 %1, 3

‎llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,9 @@ define i64 @addc_adde(i64 %a, i64 %b) nounwind {
2020
define i64 @subc_sube(i64 %a, i64 %b) nounwind {
2121
; RV32I-LABEL: subc_sube:
2222
; RV32I: # %bb.0:
23+
; RV32I-NEXT: sltu a4, a0, a2
2324
; RV32I-NEXT: sub a1, a1, a3
24-
; RV32I-NEXT: sltu a3, a0, a2
25-
; RV32I-NEXT: sub a1, a1, a3
25+
; RV32I-NEXT: sub a1, a1, a4
2626
; RV32I-NEXT: sub a0, a0, a2
2727
; RV32I-NEXT: ret
2828
%1 = sub i64 %a, %b

‎llvm/test/CodeGen/RISCV/addcarry.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -10,17 +10,17 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
1010
; RISCV32-LABEL: addcarry:
1111
; RISCV32: # %bb.0:
1212
; RISCV32-NEXT: mul a4, a0, a3
13-
; RISCV32-NEXT: mulhu a5, a0, a2
14-
; RISCV32-NEXT: add a4, a5, a4
15-
; RISCV32-NEXT: sltu a6, a4, a5
16-
; RISCV32-NEXT: mulhu a5, a0, a3
17-
; RISCV32-NEXT: add a6, a5, a6
18-
; RISCV32-NEXT: mulhu a5, a1, a2
19-
; RISCV32-NEXT: add a7, a6, a5
13+
; RISCV32-NEXT: mulhu a7, a0, a2
14+
; RISCV32-NEXT: add a4, a7, a4
2015
; RISCV32-NEXT: mul a5, a1, a2
2116
; RISCV32-NEXT: add a6, a4, a5
22-
; RISCV32-NEXT: sltu a4, a6, a4
23-
; RISCV32-NEXT: add a4, a7, a4
17+
; RISCV32-NEXT: sltu t0, a6, a4
18+
; RISCV32-NEXT: sltu a4, a4, a7
19+
; RISCV32-NEXT: mulhu a5, a0, a3
20+
; RISCV32-NEXT: add a4, a5, a4
21+
; RISCV32-NEXT: mulhu a5, a1, a2
22+
; RISCV32-NEXT: add a4, a4, a5
23+
; RISCV32-NEXT: add a4, a4, t0
2424
; RISCV32-NEXT: mul a5, a1, a3
2525
; RISCV32-NEXT: add a5, a4, a5
2626
; RISCV32-NEXT: bgez a1, .LBB0_2
@@ -31,13 +31,13 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
3131
; RISCV32-NEXT: # %bb.3:
3232
; RISCV32-NEXT: sub a5, a5, a0
3333
; RISCV32-NEXT: .LBB0_4:
34+
; RISCV32-NEXT: slli a1, a5, 30
35+
; RISCV32-NEXT: srli a3, a6, 2
36+
; RISCV32-NEXT: or a1, a1, a3
37+
; RISCV32-NEXT: slli a3, a6, 30
3438
; RISCV32-NEXT: mul a0, a0, a2
3539
; RISCV32-NEXT: srli a0, a0, 2
36-
; RISCV32-NEXT: slli a1, a6, 30
37-
; RISCV32-NEXT: or a0, a1, a0
38-
; RISCV32-NEXT: srli a1, a6, 2
39-
; RISCV32-NEXT: slli a2, a5, 30
40-
; RISCV32-NEXT: or a1, a2, a1
40+
; RISCV32-NEXT: or a0, a3, a0
4141
; RISCV32-NEXT: ret
4242
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
4343
ret i64 %tmp;

‎llvm/test/CodeGen/RISCV/alloca.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,15 +82,15 @@ define void @alloca_callframe(i32 %n) nounwind {
8282
; RV32I-NEXT: sw a1, 8(sp)
8383
; RV32I-NEXT: addi a1, zero, 10
8484
; RV32I-NEXT: sw a1, 4(sp)
85-
; RV32I-NEXT: addi a1, zero, 9
86-
; RV32I-NEXT: sw a1, 0(sp)
85+
; RV32I-NEXT: addi t0, zero, 9
8786
; RV32I-NEXT: addi a1, zero, 2
8887
; RV32I-NEXT: addi a2, zero, 3
8988
; RV32I-NEXT: addi a3, zero, 4
9089
; RV32I-NEXT: addi a4, zero, 5
9190
; RV32I-NEXT: addi a5, zero, 6
9291
; RV32I-NEXT: addi a6, zero, 7
9392
; RV32I-NEXT: addi a7, zero, 8
93+
; RV32I-NEXT: sw t0, 0(sp)
9494
; RV32I-NEXT: call func
9595
; RV32I-NEXT: addi sp, sp, 16
9696
; RV32I-NEXT: addi sp, s0, -16

‎llvm/test/CodeGen/RISCV/alu64.ll

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,8 @@ define i64 @slli(i64 %a) nounwind {
123123
;
124124
; RV32I-LABEL: slli:
125125
; RV32I: # %bb.0:
126-
; RV32I-NEXT: slli a1, a1, 7
127126
; RV32I-NEXT: srli a2, a0, 25
127+
; RV32I-NEXT: slli a1, a1, 7
128128
; RV32I-NEXT: or a1, a1, a2
129129
; RV32I-NEXT: slli a0, a0, 7
130130
; RV32I-NEXT: ret
@@ -140,8 +140,8 @@ define i64 @srli(i64 %a) nounwind {
140140
;
141141
; RV32I-LABEL: srli:
142142
; RV32I: # %bb.0:
143-
; RV32I-NEXT: srli a0, a0, 8
144143
; RV32I-NEXT: slli a2, a1, 24
144+
; RV32I-NEXT: srli a0, a0, 8
145145
; RV32I-NEXT: or a0, a0, a2
146146
; RV32I-NEXT: srli a1, a1, 8
147147
; RV32I-NEXT: ret
@@ -157,8 +157,8 @@ define i64 @srai(i64 %a) nounwind {
157157
;
158158
; RV32I-LABEL: srai:
159159
; RV32I: # %bb.0:
160-
; RV32I-NEXT: srli a0, a0, 9
161160
; RV32I-NEXT: slli a2, a1, 23
161+
; RV32I-NEXT: srli a0, a0, 9
162162
; RV32I-NEXT: or a0, a0, a2
163163
; RV32I-NEXT: srai a1, a1, 9
164164
; RV32I-NEXT: ret
@@ -194,9 +194,9 @@ define i64 @sub(i64 %a, i64 %b) nounwind {
194194
;
195195
; RV32I-LABEL: sub:
196196
; RV32I: # %bb.0:
197+
; RV32I-NEXT: sltu a4, a0, a2
197198
; RV32I-NEXT: sub a1, a1, a3
198-
; RV32I-NEXT: sltu a3, a0, a2
199-
; RV32I-NEXT: sub a1, a1, a3
199+
; RV32I-NEXT: sub a1, a1, a4
200200
; RV32I-NEXT: sub a0, a0, a2
201201
; RV32I-NEXT: ret
202202
%1 = sub i64 %a, %b
@@ -218,13 +218,14 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
218218
; RV32I-NEXT: mv a0, zero
219219
; RV32I-NEXT: ret
220220
; RV32I-NEXT: .LBB11_2:
221+
; RV32I-NEXT: sll a1, a1, a2
221222
; RV32I-NEXT: addi a3, zero, 31
222223
; RV32I-NEXT: sub a3, a3, a2
223224
; RV32I-NEXT: srli a4, a0, 1
224225
; RV32I-NEXT: srl a3, a4, a3
225-
; RV32I-NEXT: sll a1, a1, a2
226226
; RV32I-NEXT: or a1, a1, a3
227-
; RV32I-NEXT: sll a0, a0, a2
227+
; RV32I-NEXT: sll a2, a0, a2
228+
; RV32I-NEXT: mv a0, a2
228229
; RV32I-NEXT: ret
229230
%1 = shl i64 %a, %b
230231
ret i64 %1
@@ -304,13 +305,14 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
304305
; RV32I-NEXT: mv a1, zero
305306
; RV32I-NEXT: ret
306307
; RV32I-NEXT: .LBB15_2:
308+
; RV32I-NEXT: srl a0, a0, a2
307309
; RV32I-NEXT: addi a3, zero, 31
308310
; RV32I-NEXT: sub a3, a3, a2
309311
; RV32I-NEXT: slli a4, a1, 1
310312
; RV32I-NEXT: sll a3, a4, a3
311-
; RV32I-NEXT: srl a0, a0, a2
312313
; RV32I-NEXT: or a0, a0, a3
313-
; RV32I-NEXT: srl a1, a1, a2
314+
; RV32I-NEXT: srl a2, a1, a2
315+
; RV32I-NEXT: mv a1, a2
314316
; RV32I-NEXT: ret
315317
%1 = lshr i64 %a, %b
316318
ret i64 %1
@@ -331,11 +333,11 @@ define i64 @sra(i64 %a, i64 %b) nounwind {
331333
; RV32I-NEXT: srai a1, a1, 31
332334
; RV32I-NEXT: ret
333335
; RV32I-NEXT: .LBB16_2:
336+
; RV32I-NEXT: srl a0, a0, a2
334337
; RV32I-NEXT: addi a3, zero, 31
335338
; RV32I-NEXT: sub a3, a3, a2
336339
; RV32I-NEXT: slli a4, a1, 1
337340
; RV32I-NEXT: sll a3, a4, a3
338-
; RV32I-NEXT: srl a0, a0, a2
339341
; RV32I-NEXT: or a0, a0, a3
340342
; RV32I-NEXT: sra a1, a1, a2
341343
; RV32I-NEXT: ret

‎llvm/test/CodeGen/RISCV/arith-with-overflow.ll

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -10,17 +10,17 @@ declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
1010
define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind {
1111
; RV32I-LABEL: sadd:
1212
; RV32I: # %bb.0: # %entry
13-
; RV32I-NEXT: add a3, a0, a1
14-
; RV32I-NEXT: sw a3, 0(a2)
15-
; RV32I-NEXT: addi a2, zero, -1
16-
; RV32I-NEXT: slt a1, a2, a1
17-
; RV32I-NEXT: slt a0, a2, a0
18-
; RV32I-NEXT: slt a2, a2, a3
19-
; RV32I-NEXT: xor a2, a0, a2
20-
; RV32I-NEXT: xor a0, a0, a1
21-
; RV32I-NEXT: seqz a0, a0
22-
; RV32I-NEXT: snez a1, a2
23-
; RV32I-NEXT: and a0, a0, a1
13+
; RV32I-NEXT: addi a3, zero, -1
14+
; RV32I-NEXT: slt a4, a3, a1
15+
; RV32I-NEXT: slt a5, a3, a0
16+
; RV32I-NEXT: xor a4, a5, a4
17+
; RV32I-NEXT: seqz a4, a4
18+
; RV32I-NEXT: add a1, a0, a1
19+
; RV32I-NEXT: slt a0, a3, a1
20+
; RV32I-NEXT: xor a0, a5, a0
21+
; RV32I-NEXT: snez a0, a0
22+
; RV32I-NEXT: and a0, a4, a0
23+
; RV32I-NEXT: sw a1, 0(a2)
2424
; RV32I-NEXT: ret
2525
entry:
2626
%x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
@@ -33,17 +33,17 @@ entry:
3333
define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
3434
; RV32I-LABEL: ssub:
3535
; RV32I: # %bb.0: # %entry
36-
; RV32I-NEXT: sub a3, a0, a1
37-
; RV32I-NEXT: sw a3, 0(a2)
38-
; RV32I-NEXT: addi a2, zero, -1
39-
; RV32I-NEXT: slt a1, a2, a1
40-
; RV32I-NEXT: slt a0, a2, a0
41-
; RV32I-NEXT: slt a2, a2, a3
42-
; RV32I-NEXT: xor a2, a0, a2
43-
; RV32I-NEXT: xor a0, a0, a1
36+
; RV32I-NEXT: addi a3, zero, -1
37+
; RV32I-NEXT: slt a4, a3, a1
38+
; RV32I-NEXT: slt a5, a3, a0
39+
; RV32I-NEXT: xor a4, a5, a4
40+
; RV32I-NEXT: snez a4, a4
41+
; RV32I-NEXT: sub a1, a0, a1
42+
; RV32I-NEXT: slt a0, a3, a1
43+
; RV32I-NEXT: xor a0, a5, a0
4444
; RV32I-NEXT: snez a0, a0
45-
; RV32I-NEXT: snez a1, a2
46-
; RV32I-NEXT: and a0, a0, a1
45+
; RV32I-NEXT: and a0, a4, a0
46+
; RV32I-NEXT: sw a1, 0(a2)
4747
; RV32I-NEXT: ret
4848
entry:
4949
%x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
@@ -57,8 +57,8 @@ define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind {
5757
; RV32I-LABEL: uadd:
5858
; RV32I: # %bb.0: # %entry
5959
; RV32I-NEXT: add a1, a0, a1
60-
; RV32I-NEXT: sw a1, 0(a2)
6160
; RV32I-NEXT: sltu a0, a1, a0
61+
; RV32I-NEXT: sw a1, 0(a2)
6262
; RV32I-NEXT: ret
6363
entry:
6464
%x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -72,8 +72,8 @@ define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind {
7272
; RV32I-LABEL: usub:
7373
; RV32I: # %bb.0: # %entry
7474
; RV32I-NEXT: sub a1, a0, a1
75-
; RV32I-NEXT: sw a1, 0(a2)
7675
; RV32I-NEXT: sltu a0, a0, a1
76+
; RV32I-NEXT: sw a1, 0(a2)
7777
; RV32I-NEXT: ret
7878
entry:
7979
%x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)

‎llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77
; higher bits were masked to zero for the comparison.
88

99
define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
10-
i32 signext %val) nounwind {
1110
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
1211
; RV64IA: # %bb.0: # %entry
1312
; RV64IA-NEXT: .LBB0_1: # %entry
@@ -22,6 +21,7 @@ define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
2221
; RV64IA-NEXT: xor a0, a3, a1
2322
; RV64IA-NEXT: seqz a0, a0
2423
; RV64IA-NEXT: ret
24+
i32 signext %val) nounwind {
2525
entry:
2626
%0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
2727
%1 = extractvalue { i32, i1 } %0, 1

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