Skip to content

Commit 3da2a87

Browse files
author
git apple-llvm automerger
committed
Merge commit 'aefedb170734' from llvm.org/master into apple/main
2 parents 9f72fd6 + aefedb1 commit 3da2a87

File tree

13 files changed

+352
-0
lines changed

13 files changed

+352
-0
lines changed

‎llvm/include/llvm/IR/IntrinsicsVEVL.gen.td

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1196,3 +1196,18 @@ let TargetPrefix = "ve" in def int_ve_vl_vsclot_vvssl : GCCBuiltin<"__builtin_ve
11961196
let TargetPrefix = "ve" in def int_ve_vl_vsclot_vvssml : GCCBuiltin<"__builtin_ve_vl_vsclot_vvssml">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i64>, LLVMType<i64>, LLVMType<v256i1>, LLVMType<i32>], [IntrWriteMem]>;
11971197
let TargetPrefix = "ve" in def int_ve_vl_vsclncot_vvssl : GCCBuiltin<"__builtin_ve_vl_vsclncot_vvssl">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i64>, LLVMType<i64>, LLVMType<i32>], [IntrWriteMem]>;
11981198
let TargetPrefix = "ve" in def int_ve_vl_vsclncot_vvssml : GCCBuiltin<"__builtin_ve_vl_vsclncot_vvssml">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i64>, LLVMType<i64>, LLVMType<v256i1>, LLVMType<i32>], [IntrWriteMem]>;
1199+
let TargetPrefix = "ve" in def int_ve_vl_andm_mmm : GCCBuiltin<"__builtin_ve_vl_andm_mmm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<v256i1>], [IntrNoMem]>;
1200+
let TargetPrefix = "ve" in def int_ve_vl_andm_MMM : GCCBuiltin<"__builtin_ve_vl_andm_MMM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<v512i1>], [IntrNoMem]>;
1201+
let TargetPrefix = "ve" in def int_ve_vl_orm_mmm : GCCBuiltin<"__builtin_ve_vl_orm_mmm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<v256i1>], [IntrNoMem]>;
1202+
let TargetPrefix = "ve" in def int_ve_vl_orm_MMM : GCCBuiltin<"__builtin_ve_vl_orm_MMM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<v512i1>], [IntrNoMem]>;
1203+
let TargetPrefix = "ve" in def int_ve_vl_xorm_mmm : GCCBuiltin<"__builtin_ve_vl_xorm_mmm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<v256i1>], [IntrNoMem]>;
1204+
let TargetPrefix = "ve" in def int_ve_vl_xorm_MMM : GCCBuiltin<"__builtin_ve_vl_xorm_MMM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<v512i1>], [IntrNoMem]>;
1205+
let TargetPrefix = "ve" in def int_ve_vl_eqvm_mmm : GCCBuiltin<"__builtin_ve_vl_eqvm_mmm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<v256i1>], [IntrNoMem]>;
1206+
let TargetPrefix = "ve" in def int_ve_vl_eqvm_MMM : GCCBuiltin<"__builtin_ve_vl_eqvm_MMM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<v512i1>], [IntrNoMem]>;
1207+
let TargetPrefix = "ve" in def int_ve_vl_nndm_mmm : GCCBuiltin<"__builtin_ve_vl_nndm_mmm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<v256i1>], [IntrNoMem]>;
1208+
let TargetPrefix = "ve" in def int_ve_vl_nndm_MMM : GCCBuiltin<"__builtin_ve_vl_nndm_MMM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<v512i1>], [IntrNoMem]>;
1209+
let TargetPrefix = "ve" in def int_ve_vl_negm_mm : GCCBuiltin<"__builtin_ve_vl_negm_mm">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>], [IntrNoMem]>;
1210+
let TargetPrefix = "ve" in def int_ve_vl_negm_MM : GCCBuiltin<"__builtin_ve_vl_negm_MM">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>], [IntrNoMem]>;
1211+
let TargetPrefix = "ve" in def int_ve_vl_pcvm_sml : GCCBuiltin<"__builtin_ve_vl_pcvm_sml">, Intrinsic<[LLVMType<i64>], [LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
1212+
let TargetPrefix = "ve" in def int_ve_vl_lzvm_sml : GCCBuiltin<"__builtin_ve_vl_lzvm_sml">, Intrinsic<[LLVMType<i64>], [LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
1213+
let TargetPrefix = "ve" in def int_ve_vl_tovm_sml : GCCBuiltin<"__builtin_ve_vl_tovm_sml">, Intrinsic<[LLVMType<i64>], [LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;

‎llvm/lib/Target/VE/VEInstrInfo.cpp

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -731,6 +731,32 @@ static Register getVM512Upper(Register reg) {
731731

732732
static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; }
733733

734+
// Expand pseudo logical vector instructions for VM512 registers.
735+
static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID) {
736+
MachineBasicBlock *MBB = MI.getParent();
737+
DebugLoc DL = MI.getDebugLoc();
738+
739+
Register VMXu = getVM512Upper(MI.getOperand(0).getReg());
740+
Register VMXl = getVM512Lower(MI.getOperand(0).getReg());
741+
Register VMYu = getVM512Upper(MI.getOperand(1).getReg());
742+
Register VMYl = getVM512Lower(MI.getOperand(1).getReg());
743+
744+
switch (MI.getOpcode()) {
745+
default: {
746+
Register VMZu = getVM512Upper(MI.getOperand(2).getReg());
747+
Register VMZl = getVM512Lower(MI.getOperand(2).getReg());
748+
BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu);
749+
BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl);
750+
break;
751+
}
752+
case VE::NEGMy:
753+
BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu);
754+
BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl);
755+
break;
756+
}
757+
MI.eraseFromParent();
758+
}
759+
734760
static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI,
735761
bool Upper) {
736762
// VM512
@@ -812,6 +838,25 @@ bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
812838
return expandGetStackTopPseudo(MI);
813839
}
814840

841+
case VE::ANDMyy:
842+
expandPseudoLogM(MI, get(VE::ANDMmm));
843+
return true;
844+
case VE::ORMyy:
845+
expandPseudoLogM(MI, get(VE::ORMmm));
846+
return true;
847+
case VE::XORMyy:
848+
expandPseudoLogM(MI, get(VE::XORMmm));
849+
return true;
850+
case VE::EQVMyy:
851+
expandPseudoLogM(MI, get(VE::EQVMmm));
852+
return true;
853+
case VE::NNDMyy:
854+
expandPseudoLogM(MI, get(VE::NNDMmm));
855+
return true;
856+
case VE::NEGMy:
857+
expandPseudoLogM(MI, get(VE::NEGMm));
858+
return true;
859+
815860
case VE::LVMyir:
816861
case VE::LVMyim:
817862
case VE::LVMyir_y:

‎llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1587,3 +1587,18 @@ def : Pat<(int_ve_vl_vsclncot_vvssml v256f64:$vx, v256f64:$vy, i64:$sy, i64:$sz,
15871587
def : Pat<(int_ve_vl_vsclncot_vvssml v256f64:$vx, v256f64:$vy, i64:$sy, zero:$Z, v256i1:$vm, i32:$vl), (VSCLNCOTvrzvml v256f64:$vy, i64:$sy, (LO7 $Z), v256f64:$vx, v256i1:$vm, i32:$vl)>;
15881588
def : Pat<(int_ve_vl_vsclncot_vvssml v256f64:$vx, v256f64:$vy, simm7:$I, i64:$sz, v256i1:$vm, i32:$vl), (VSCLNCOTvirvml v256f64:$vy, (LO7 $I), i64:$sz, v256f64:$vx, v256i1:$vm, i32:$vl)>;
15891589
def : Pat<(int_ve_vl_vsclncot_vvssml v256f64:$vx, v256f64:$vy, simm7:$I, zero:$Z, v256i1:$vm, i32:$vl), (VSCLNCOTvizvml v256f64:$vy, (LO7 $I), (LO7 $Z), v256f64:$vx, v256i1:$vm, i32:$vl)>;
1590+
def : Pat<(int_ve_vl_andm_mmm v256i1:$vmy, v256i1:$vmz), (ANDMmm v256i1:$vmy, v256i1:$vmz)>;
1591+
def : Pat<(int_ve_vl_andm_MMM v512i1:$vmy, v512i1:$vmz), (ANDMyy v512i1:$vmy, v512i1:$vmz)>;
1592+
def : Pat<(int_ve_vl_orm_mmm v256i1:$vmy, v256i1:$vmz), (ORMmm v256i1:$vmy, v256i1:$vmz)>;
1593+
def : Pat<(int_ve_vl_orm_MMM v512i1:$vmy, v512i1:$vmz), (ORMyy v512i1:$vmy, v512i1:$vmz)>;
1594+
def : Pat<(int_ve_vl_xorm_mmm v256i1:$vmy, v256i1:$vmz), (XORMmm v256i1:$vmy, v256i1:$vmz)>;
1595+
def : Pat<(int_ve_vl_xorm_MMM v512i1:$vmy, v512i1:$vmz), (XORMyy v512i1:$vmy, v512i1:$vmz)>;
1596+
def : Pat<(int_ve_vl_eqvm_mmm v256i1:$vmy, v256i1:$vmz), (EQVMmm v256i1:$vmy, v256i1:$vmz)>;
1597+
def : Pat<(int_ve_vl_eqvm_MMM v512i1:$vmy, v512i1:$vmz), (EQVMyy v512i1:$vmy, v512i1:$vmz)>;
1598+
def : Pat<(int_ve_vl_nndm_mmm v256i1:$vmy, v256i1:$vmz), (NNDMmm v256i1:$vmy, v256i1:$vmz)>;
1599+
def : Pat<(int_ve_vl_nndm_MMM v512i1:$vmy, v512i1:$vmz), (NNDMyy v512i1:$vmy, v512i1:$vmz)>;
1600+
def : Pat<(int_ve_vl_negm_mm v256i1:$vmy), (NEGMm v256i1:$vmy)>;
1601+
def : Pat<(int_ve_vl_negm_MM v512i1:$vmy), (NEGMy v512i1:$vmy)>;
1602+
def : Pat<(int_ve_vl_pcvm_sml v256i1:$vmy, i32:$vl), (PCVMml v256i1:$vmy, i32:$vl)>;
1603+
def : Pat<(int_ve_vl_lzvm_sml v256i1:$vmy, i32:$vl), (LZVMml v256i1:$vmy, i32:$vl)>;
1604+
def : Pat<(int_ve_vl_tovm_sml v256i1:$vmy, i32:$vl), (TOVMml v256i1:$vmy, i32:$vl)>;

‎llvm/lib/Target/VE/VEInstrVec.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,22 @@ let hasSideEffects = 0, isCodeGenOnly = 1, DisableEncoding = "$vl" in {
4343
"# pseudo-vfmk.s.$cf $vmx, $vz, $vm">;
4444
}
4545

46+
// ANDM/ORM/XORM/EQVM/NNDM/NEGM instructions using VM512
47+
let hasSideEffects = 0, isCodeGenOnly = 1 in {
48+
def ANDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
49+
"# andm $vmx, $vmy, $vmz">;
50+
def ORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
51+
"# orm $vmx, $vmy, $vmz">;
52+
def XORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
53+
"# xorm $vmx, $vmy, $vmz">;
54+
def EQVMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
55+
"# eqvm $vmx, $vmy, $vmz">;
56+
def NNDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
57+
"# nndm $vmx, $vmy, $vmz">;
58+
def NEGMy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy),
59+
"# negm $vmx, $vmy">;
60+
}
61+
4662
//===----------------------------------------------------------------------===//
4763
// Instructions
4864
//

‎llvm/test/CodeGen/VE/VELIntrinsics/andm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test and vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test ANDM*mm and ANDM*yy instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @andm_mmm(<256 x i1> %0, <256 x i1> %1) {
10+
; CHECK-LABEL: andm_mmm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: andm %vm1, %vm1, %vm2
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%3 = tail call <256 x i1> @llvm.ve.vl.andm.mmm(<256 x i1> %0, <256 x i1> %1)
15+
ret <256 x i1> %3
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.andm.mmm(<256 x i1>, <256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @andm_MMM(<512 x i1> %0, <512 x i1> %1) {
23+
; CHECK-LABEL: andm_MMM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: andm %vm2, %vm2, %vm4
26+
; CHECK-NEXT: andm %vm3, %vm3, %vm5
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%3 = tail call <512 x i1> @llvm.ve.vl.andm.MMM(<512 x i1> %0, <512 x i1> %1)
29+
ret <512 x i1> %3
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.andm.MMM(<512 x i1>, <512 x i1>)

‎llvm/test/CodeGen/VE/VELIntrinsics/eqvm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test equivalence vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test EQVM*mm and EQVM*yy instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @eqvm_mmm(<256 x i1> %0, <256 x i1> %1) {
10+
; CHECK-LABEL: eqvm_mmm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: eqvm %vm1, %vm1, %vm2
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%3 = tail call <256 x i1> @llvm.ve.vl.eqvm.mmm(<256 x i1> %0, <256 x i1> %1)
15+
ret <256 x i1> %3
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.eqvm.mmm(<256 x i1>, <256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @eqvm_MMM(<512 x i1> %0, <512 x i1> %1) {
23+
; CHECK-LABEL: eqvm_MMM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: eqvm %vm2, %vm2, %vm4
26+
; CHECK-NEXT: eqvm %vm3, %vm3, %vm5
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%3 = tail call <512 x i1> @llvm.ve.vl.eqvm.MMM(<512 x i1> %0, <512 x i1> %1)
29+
ret <512 x i1> %3
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.eqvm.MMM(<512 x i1>, <512 x i1>)

‎llvm/test/CodeGen/VE/VELIntrinsics/lzvm.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test leading zero of vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test LZVM*ml instruction.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc i64 @lzvm_sml(<256 x i1> %0) {
10+
; CHECK-LABEL: lzvm_sml:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: lea %s0, 256
13+
; CHECK-NEXT: lvl %s0
14+
; CHECK-NEXT: lzvm %s0, %vm1
15+
; CHECK-NEXT: b.l.t (, %s10)
16+
%2 = tail call i64 @llvm.ve.vl.lzvm.sml(<256 x i1> %0, i32 256)
17+
ret i64 %2
18+
}
19+
20+
; Function Attrs: nounwind readnone
21+
declare i64 @llvm.ve.vl.lzvm.sml(<256 x i1>, i32)

‎llvm/test/CodeGen/VE/VELIntrinsics/negm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test negate vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test NEGM*m and NEGM*y instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @negm_mm(<256 x i1> %0) {
10+
; CHECK-LABEL: negm_mm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: negm %vm1, %vm1
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%2 = tail call <256 x i1> @llvm.ve.vl.negm.mm(<256 x i1> %0)
15+
ret <256 x i1> %2
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.negm.mm(<256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @negm_MM(<512 x i1> %0) {
23+
; CHECK-LABEL: negm_MM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: negm %vm2, %vm2
26+
; CHECK-NEXT: negm %vm3, %vm3
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%2 = tail call <512 x i1> @llvm.ve.vl.negm.MM(<512 x i1> %0)
29+
ret <512 x i1> %2
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.negm.MM(<512 x i1>)

‎llvm/test/CodeGen/VE/VELIntrinsics/nndm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test negate and vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test NNDM*mm and NNDM*yy instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @nndm_mmm(<256 x i1> %0, <256 x i1> %1) {
10+
; CHECK-LABEL: nndm_mmm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: nndm %vm1, %vm1, %vm2
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%3 = tail call <256 x i1> @llvm.ve.vl.nndm.mmm(<256 x i1> %0, <256 x i1> %1)
15+
ret <256 x i1> %3
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.nndm.mmm(<256 x i1>, <256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @nndm_MMM(<512 x i1> %0, <512 x i1> %1) {
23+
; CHECK-LABEL: nndm_MMM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: nndm %vm2, %vm2, %vm4
26+
; CHECK-NEXT: nndm %vm3, %vm3, %vm5
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%3 = tail call <512 x i1> @llvm.ve.vl.nndm.MMM(<512 x i1> %0, <512 x i1> %1)
29+
ret <512 x i1> %3
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.nndm.MMM(<512 x i1>, <512 x i1>)

‎llvm/test/CodeGen/VE/VELIntrinsics/orm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test or vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test ORM*mm and ORM*yy instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @orm_mmm(<256 x i1> %0, <256 x i1> %1) {
10+
; CHECK-LABEL: orm_mmm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: orm %vm1, %vm1, %vm2
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%3 = tail call <256 x i1> @llvm.ve.vl.orm.mmm(<256 x i1> %0, <256 x i1> %1)
15+
ret <256 x i1> %3
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.orm.mmm(<256 x i1>, <256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @orm_MMM(<512 x i1> %0, <512 x i1> %1) {
23+
; CHECK-LABEL: orm_MMM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: orm %vm2, %vm2, %vm4
26+
; CHECK-NEXT: orm %vm3, %vm3, %vm5
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%3 = tail call <512 x i1> @llvm.ve.vl.orm.MMM(<512 x i1> %0, <512 x i1> %1)
29+
ret <512 x i1> %3
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.orm.MMM(<512 x i1>, <512 x i1>)

‎llvm/test/CodeGen/VE/VELIntrinsics/pcvm.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test population count of vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test PCVM*ml instruction.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc i64 @pcvm_sml(<256 x i1> %0) {
10+
; CHECK-LABEL: pcvm_sml:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: lea %s0, 256
13+
; CHECK-NEXT: lvl %s0
14+
; CHECK-NEXT: pcvm %s0, %vm1
15+
; CHECK-NEXT: b.l.t (, %s10)
16+
%2 = tail call i64 @llvm.ve.vl.pcvm.sml(<256 x i1> %0, i32 256)
17+
ret i64 %2
18+
}
19+
20+
; Function Attrs: nounwind readnone
21+
declare i64 @llvm.ve.vl.pcvm.sml(<256 x i1>, i32)

‎llvm/test/CodeGen/VE/VELIntrinsics/tovm.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test trailing one of vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test TOVM*ml instruction.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc i64 @tovm_sml(<256 x i1> %0) {
10+
; CHECK-LABEL: tovm_sml:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: lea %s0, 256
13+
; CHECK-NEXT: lvl %s0
14+
; CHECK-NEXT: tovm %s0, %vm1
15+
; CHECK-NEXT: b.l.t (, %s10)
16+
%2 = tail call i64 @llvm.ve.vl.tovm.sml(<256 x i1> %0, i32 256)
17+
ret i64 %2
18+
}
19+
20+
; Function Attrs: nounwind readnone
21+
declare i64 @llvm.ve.vl.tovm.sml(<256 x i1>, i32)

‎llvm/test/CodeGen/VE/VELIntrinsics/xorm.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2+
3+
;;; Test exclusive or vm intrinsic instructions
4+
;;;
5+
;;; Note:
6+
;;; We test XORM*mm and XORM*yy instructions.
7+
8+
; Function Attrs: nounwind readnone
9+
define fastcc <256 x i1> @xorm_mmm(<256 x i1> %0, <256 x i1> %1) {
10+
; CHECK-LABEL: xorm_mmm:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: xorm %vm1, %vm1, %vm2
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%3 = tail call <256 x i1> @llvm.ve.vl.xorm.mmm(<256 x i1> %0, <256 x i1> %1)
15+
ret <256 x i1> %3
16+
}
17+
18+
; Function Attrs: nounwind readnone
19+
declare <256 x i1> @llvm.ve.vl.xorm.mmm(<256 x i1>, <256 x i1>)
20+
21+
; Function Attrs: nounwind readnone
22+
define fastcc <512 x i1> @xorm_MMM(<512 x i1> %0, <512 x i1> %1) {
23+
; CHECK-LABEL: xorm_MMM:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: xorm %vm2, %vm2, %vm4
26+
; CHECK-NEXT: xorm %vm3, %vm3, %vm5
27+
; CHECK-NEXT: b.l.t (, %s10)
28+
%3 = tail call <512 x i1> @llvm.ve.vl.xorm.MMM(<512 x i1> %0, <512 x i1> %1)
29+
ret <512 x i1> %3
30+
}
31+
32+
; Function Attrs: nounwind readnone
33+
declare <512 x i1> @llvm.ve.vl.xorm.MMM(<512 x i1>, <512 x i1>)

0 commit comments

Comments
 (0)