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[Support][SelectionDAG][GlobalISel] Hoist PostShift adjustment for IsAdd into UnsignedDivideUsingMagic.
Instead of doing the adjustment in 3 different places in the code base, do it inside UnsignedDivideUsingMagic::get. Differential Revision: https://reviews.llvm.org/D141014
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5 files changed

+32
-38
lines changed

5 files changed

+32
-38
lines changed

llvm/include/llvm/Support/DivisionByConstantInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ struct UnsignedDivisionByConstantInfo {
3131
bool AllowEvenDivisorOptimization = true);
3232
APInt Magic; ///< magic number
3333
bool IsAdd; ///< add indicator
34-
unsigned ShiftAmount; ///< shift amount
34+
unsigned PostShift; ///< post-shift amount
3535
unsigned PreShift; ///< pre-shift amount
3636
};
3737

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4962,16 +4962,14 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
49624962

49634963
Magic = std::move(magics.Magic);
49644964

4965-
if (!magics.IsAdd) {
4966-
assert(magics.ShiftAmount < Divisor.getBitWidth() &&
4967-
"We shouldn't generate an undefined shift!");
4968-
PostShift = magics.ShiftAmount;
4969-
PreShift = magics.PreShift;
4970-
} else {
4971-
assert(magics.PreShift == 0 && "Unexpected pre-shift");
4972-
PostShift = magics.ShiftAmount - 1;
4973-
SelNPQ = true;
4974-
}
4965+
assert(magics.PreShift < Divisor.getBitWidth() &&
4966+
"We shouldn't generate an undefined shift!");
4967+
assert(magics.PostShift < Divisor.getBitWidth() &&
4968+
"We shouldn't generate an undefined shift!");
4969+
assert((!magics.IsAdd || magics.PreShift == 0) && "Unexpected pre-shift");
4970+
PreShift = magics.PreShift;
4971+
PostShift = magics.PostShift;
4972+
SelNPQ = magics.IsAdd;
49754973
}
49764974

49774975
PreShifts.push_back(

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6056,16 +6056,15 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
60566056

60576057
Magic = std::move(magics.Magic);
60586058

6059-
if (!magics.IsAdd) {
6060-
assert(magics.ShiftAmount < Divisor.getBitWidth() &&
6061-
"We shouldn't generate an undefined shift!");
6062-
PostShift = magics.ShiftAmount;
6063-
PreShift = magics.PreShift;
6064-
} else {
6065-
assert(magics.PreShift == 0 && "Unexpected pre-shift");
6066-
PostShift = magics.ShiftAmount - 1;
6067-
SelNPQ = true;
6068-
}
6059+
assert(magics.PreShift < Divisor.getBitWidth() &&
6060+
"We shouldn't generate an undefined shift!");
6061+
assert(magics.PostShift < Divisor.getBitWidth() &&
6062+
"We shouldn't generate an undefined shift!");
6063+
assert((!magics.IsAdd || magics.PreShift == 0) &&
6064+
"Unexpected pre-shift");
6065+
PreShift = magics.PreShift;
6066+
PostShift = magics.PostShift;
6067+
SelNPQ = magics.IsAdd;
60696068
}
60706069

60716070
PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT));

llvm/lib/Support/DivisionByConstantInfo.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,12 @@ UnsignedDivisionByConstantInfo::get(const APInt &D, unsigned LeadingZeros,
143143

144144
Retval.Magic = std::move(Q2); // resulting magic number
145145
++Retval.Magic;
146-
Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift
146+
Retval.PostShift = P - D.getBitWidth(); // resulting shift
147+
// Reduce shift amount for IsAdd.
148+
if (Retval.IsAdd) {
149+
assert(Retval.PostShift > 0 && "Unexpected shift");
150+
Retval.PostShift -= 1;
151+
}
147152
Retval.PreShift = 0;
148153
return Retval;
149154
}

llvm/unittests/Support/DivisionByConstantTest.cpp

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -116,22 +116,14 @@ APInt UnsignedDivideUsingMagic(const APInt &Numerator, const APInt &Divisor,
116116
}
117117
}
118118

119-
unsigned PreShift = 0;
120-
unsigned PostShift = 0;
121-
bool UseNPQ = false;
122-
if (!Magics.IsAdd) {
123-
assert(Magics.ShiftAmount < Divisor.getBitWidth() &&
124-
"We shouldn't generate an undefined shift!");
125-
PreShift = Magics.PreShift;
126-
PostShift = Magics.ShiftAmount;
127-
UseNPQ = false;
128-
} else {
129-
assert(Magics.PreShift == 0 && "Unexpected pre-shift");
130-
PostShift = Magics.ShiftAmount - 1;
131-
assert(PostShift < Divisor.getBitWidth() &&
132-
"We shouldn't generate an undefined shift!");
133-
UseNPQ = true;
134-
}
119+
assert(Magics.PreShift < Divisor.getBitWidth() &&
120+
"We shouldn't generate an undefined shift!");
121+
assert(Magics.PostShift < Divisor.getBitWidth() &&
122+
"We shouldn't generate an undefined shift!");
123+
assert((!Magics.IsAdd || Magics.PreShift == 0) && "Unexpected pre-shift");
124+
unsigned PreShift = Magics.PreShift;
125+
unsigned PostShift = Magics.PostShift;
126+
bool UseNPQ = Magics.IsAdd;
135127

136128
APInt NPQFactor =
137129
UseNPQ ? APInt::getSignedMinValue(Bits) : APInt::getZero(Bits);

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