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[InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow
It would be already handled by the non-inverted case if we were hoisting the `not` in InstCombine, but we don't (granted, we don't sink it in this case either), so this is a separate case. llvm-svn: 366801
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‎llvm/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov-not.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instsimplify -S | FileCheck %s
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declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #1
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define i1 @t0_umul(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t0_umul(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @t1_commutative(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t1_commutative(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[PHITMP]], [[CMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %phitmp, %cmp ; swapped
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ret i1 %or
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}
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define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
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; CHECK-LABEL: @n2_wrong_size(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE1:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size1, 0 ; not %size0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n3_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp ne i4 %size, 0 ; not 'eq'
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n4_not_and(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n4_not_and(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = and i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = and i1 %cmp, %phitmp ; not 'or'
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ret i1 %or
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}
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define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n5_not_zero(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 1
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 1 ; should be '0'
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}

‎llvm/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov-not.ll

Lines changed: 106 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instsimplify -S | FileCheck %s
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declare { i4, i1 } @llvm.umul.with.overflow.i4(i4, i4) #1
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define i1 @t0_umul(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t0_umul(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @t1_commutative(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t1_commutative(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[PHITMP]], [[CMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = or i1 %phitmp, %cmp ; swapped
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ret i1 %or
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}
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define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
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; CHECK-LABEL: @n2_wrong_size(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE1:%.*]], 0
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size1, 0 ; not %size0
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size0, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n3_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp ne i4 %size, 0 ; not 'eq'
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n4_not_and(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n4_not_and(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = and i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = and i1 %cmp, %phitmp ; not 'or'
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ret i1 %or
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}
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define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n5_not_zero(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 1
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; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[UMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 1 ; should be '0'
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%umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
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%umul.ov = extractvalue { i4, i1 } %umul, 1
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%phitmp = xor i1 %umul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}

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