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Petar AvramovicPetar Avramovic
Petar Avramovic
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Petar Avramovic
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[MIPS GlobalISel] Select MSA vector generic and builtin fsqrt
selectImpl is able to select G_FSQRT when we set bank for vector operands to fprb. Add detailed tests. Note: G_FSQRT is generated from llvm-ir intrinsics llvm.sqrt.*, and at the moment MIPS is not able to generate this intrinsic for vector type (some targets generate vector llvm.sqrt.* from calls to a builtin function). __builtin_msa_fsqrt_<format> will be transformed into G_FSQRT in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69376
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8 files changed

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lines changed

8 files changed

+320
-7
lines changed

‎llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -188,10 +188,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
188188
getActionDefinitionsBuilder(G_FCONSTANT)
189189
.legalFor({s32, s64});
190190

191-
getActionDefinitionsBuilder(G_FSQRT)
192-
.legalFor({s32, s64});
193-
194-
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
191+
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
195192
.legalIf([=, &ST](const LegalityQuery &Query) {
196193
if (CheckTyN(0, Query, {s32, s64}))
197194
return true;
@@ -326,6 +323,17 @@ static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
326323
return true;
327324
}
328325

326+
bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
327+
MachineIRBuilder &MIRBuilder,
328+
const MipsSubtarget &ST) {
329+
assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
330+
MIRBuilder.buildInstr(Opcode)
331+
.add(MI.getOperand(0))
332+
.add(MI.getOperand(2));
333+
MI.eraseFromParent();
334+
return true;
335+
}
336+
329337
bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
330338
MachineRegisterInfo &MRI,
331339
MachineIRBuilder &MIRBuilder) const {
@@ -429,6 +437,10 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
429437
return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
430438
case Intrinsic::mips_fmax_a_d:
431439
return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
440+
case Intrinsic::mips_fsqrt_w:
441+
return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
442+
case Intrinsic::mips_fsqrt_d:
443+
return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
432444
default:
433445
break;
434446
}

‎llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -539,14 +539,12 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
539539
&Mips::ValueMappings[Mips::GPRIdx]});
540540
MappingID = CustomMappingID;
541541
break;
542-
case G_FSQRT:
543-
OperandsMapping = getFprbMapping(Op0Size);
544-
break;
545542
case G_FADD:
546543
case G_FSUB:
547544
case G_FMUL:
548545
case G_FDIV:
549546
case G_FABS:
547+
case G_FSQRT:
550548
OperandsMapping = getFprbMapping(Op0Size);
551549
if (Op0Size == 128)
552550
OperandsMapping = getMSAMapping(MF);

‎llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3+
--- |
4+
5+
define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
6+
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
7+
8+
...
9+
---
10+
name: sqrt_v4f32
11+
alignment: 4
12+
legalized: true
13+
regBankSelected: true
14+
tracksRegLiveness: true
15+
body: |
16+
bb.1.entry:
17+
liveins: $a0, $a1
18+
19+
; P5600-LABEL: name: sqrt_v4f32
20+
; P5600: liveins: $a0, $a1
21+
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
22+
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
23+
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
24+
; P5600: [[FSQRT_W:%[0-9]+]]:msa128w = FSQRT_W [[LD_W]]
25+
; P5600: ST_W [[FSQRT_W]], [[COPY1]], 0 :: (store 16 into %ir.c)
26+
; P5600: RetRA
27+
%0:gprb(p0) = COPY $a0
28+
%1:gprb(p0) = COPY $a1
29+
%2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
30+
%3:fprb(<4 x s32>) = G_FSQRT %2
31+
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
32+
RetRA
33+
34+
...
35+
---
36+
name: sqrt_v2f64
37+
alignment: 4
38+
legalized: true
39+
regBankSelected: true
40+
tracksRegLiveness: true
41+
body: |
42+
bb.1.entry:
43+
liveins: $a0, $a1
44+
45+
; P5600-LABEL: name: sqrt_v2f64
46+
; P5600: liveins: $a0, $a1
47+
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
48+
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
49+
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
50+
; P5600: [[FSQRT_D:%[0-9]+]]:msa128d = FSQRT_D [[LD_D]]
51+
; P5600: ST_D [[FSQRT_D]], [[COPY1]], 0 :: (store 16 into %ir.c)
52+
; P5600: RetRA
53+
%0:gprb(p0) = COPY $a0
54+
%1:gprb(p0) = COPY $a1
55+
%2:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
56+
%3:fprb(<2 x s64>) = G_FSQRT %2
57+
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
58+
RetRA
59+
60+
...

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3+
--- |
4+
5+
define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
6+
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
7+
8+
...
9+
---
10+
name: sqrt_v4f32
11+
alignment: 4
12+
tracksRegLiveness: true
13+
body: |
14+
bb.1.entry:
15+
liveins: $a0, $a1
16+
17+
; P5600-LABEL: name: sqrt_v4f32
18+
; P5600: liveins: $a0, $a1
19+
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
20+
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
21+
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
22+
; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
23+
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
24+
; P5600: RetRA
25+
%0:_(p0) = COPY $a0
26+
%1:_(p0) = COPY $a1
27+
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
28+
%3:_(<4 x s32>) = G_FSQRT %2
29+
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
30+
RetRA
31+
32+
...
33+
---
34+
name: sqrt_v2f64
35+
alignment: 4
36+
tracksRegLiveness: true
37+
body: |
38+
bb.1.entry:
39+
liveins: $a0, $a1
40+
41+
; P5600-LABEL: name: sqrt_v2f64
42+
; P5600: liveins: $a0, $a1
43+
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
44+
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
45+
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
46+
; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
47+
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
48+
; P5600: RetRA
49+
%0:_(p0) = COPY $a0
50+
%1:_(p0) = COPY $a1
51+
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
52+
%3:_(<2 x s64>) = G_FSQRT %2
53+
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
54+
RetRA
55+
56+
...

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3+
--- |
4+
5+
declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>)
6+
define void @fsqrt_v4f32_builtin(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
7+
8+
declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>)
9+
define void @fsqrt_v2f64_builtin(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
10+
11+
...
12+
---
13+
name: fsqrt_v4f32_builtin
14+
alignment: 4
15+
tracksRegLiveness: true
16+
body: |
17+
bb.1.entry:
18+
liveins: $a0, $a1
19+
20+
; P5600-LABEL: name: fsqrt_v4f32_builtin
21+
; P5600: liveins: $a0, $a1
22+
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
23+
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
24+
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
25+
; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
26+
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
27+
; P5600: RetRA
28+
%0:_(p0) = COPY $a0
29+
%1:_(p0) = COPY $a1
30+
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
31+
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fsqrt.w), %2(<4 x s32>)
32+
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
33+
RetRA
34+
35+
...
36+
---
37+
name: fsqrt_v2f64_builtin
38+
alignment: 4
39+
tracksRegLiveness: true
40+
body: |
41+
bb.1.entry:
42+
liveins: $a0, $a1
43+
44+
; P5600-LABEL: name: fsqrt_v2f64_builtin
45+
; P5600: liveins: $a0, $a1
46+
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
47+
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
48+
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
49+
; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
50+
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
51+
; P5600: RetRA
52+
%0:_(p0) = COPY $a0
53+
%1:_(p0) = COPY $a1
54+
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
55+
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fsqrt.d), %2(<2 x s64>)
56+
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
57+
RetRA
58+
59+
...
60+

‎llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt_vec.ll

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
3+
4+
declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)
5+
define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) {
6+
; P5600-LABEL: sqrt_v4f32:
7+
; P5600: # %bb.0: # %entry
8+
; P5600-NEXT: ld.w $w0, 0($4)
9+
; P5600-NEXT: fsqrt.w $w0, $w0
10+
; P5600-NEXT: st.w $w0, 0($5)
11+
; P5600-NEXT: jr $ra
12+
; P5600-NEXT: nop
13+
entry:
14+
%0 = load <4 x float>, <4 x float>* %a, align 16
15+
%sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %0)
16+
store <4 x float> %sqrt, <4 x float>* %c, align 16
17+
ret void
18+
}
19+
20+
declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)
21+
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) {
22+
; P5600-LABEL: sqrt_v2f64:
23+
; P5600: # %bb.0: # %entry
24+
; P5600-NEXT: ld.d $w0, 0($4)
25+
; P5600-NEXT: fsqrt.d $w0, $w0
26+
; P5600-NEXT: st.d $w0, 0($5)
27+
; P5600-NEXT: jr $ra
28+
; P5600-NEXT: nop
29+
entry:
30+
%0 = load <2 x double>, <2 x double>* %a, align 16
31+
%sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %0)
32+
store <2 x double> %sqrt, <2 x double>* %c, align 16
33+
ret void
34+
}

‎llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt_vec_builtin.ll

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
3+
4+
declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>)
5+
define void @fsqrt_v4f32_builtin(<4 x float>* %a, <4 x float>* %c) {
6+
; P5600-LABEL: fsqrt_v4f32_builtin:
7+
; P5600: # %bb.0: # %entry
8+
; P5600-NEXT: ld.w $w0, 0($4)
9+
; P5600-NEXT: fsqrt.w $w0, $w0
10+
; P5600-NEXT: st.w $w0, 0($5)
11+
; P5600-NEXT: jr $ra
12+
; P5600-NEXT: nop
13+
entry:
14+
%0 = load <4 x float>, <4 x float>* %a, align 16
15+
%1 = tail call <4 x float> @llvm.mips.fsqrt.w(<4 x float> %0)
16+
store <4 x float> %1, <4 x float>* %c, align 16
17+
ret void
18+
}
19+
20+
declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>)
21+
define void @fsqrt_v2f64_builtin(<2 x double>* %a, <2 x double>* %c) {
22+
; P5600-LABEL: fsqrt_v2f64_builtin:
23+
; P5600: # %bb.0: # %entry
24+
; P5600-NEXT: ld.d $w0, 0($4)
25+
; P5600-NEXT: fsqrt.d $w0, $w0
26+
; P5600-NEXT: st.d $w0, 0($5)
27+
; P5600-NEXT: jr $ra
28+
; P5600-NEXT: nop
29+
entry:
30+
%0 = load <2 x double>, <2 x double>* %a, align 16
31+
%1 = tail call <2 x double> @llvm.mips.fsqrt.d(<2 x double> %0)
32+
store <2 x double> %1, <2 x double>* %c, align 16
33+
ret void
34+
}
35+

‎llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3+
--- |
4+
5+
define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
6+
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
7+
8+
...
9+
---
10+
name: sqrt_v4f32
11+
alignment: 4
12+
legalized: true
13+
tracksRegLiveness: true
14+
body: |
15+
bb.1.entry:
16+
liveins: $a0, $a1
17+
18+
; P5600-LABEL: name: sqrt_v4f32
19+
; P5600: liveins: $a0, $a1
20+
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
21+
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
22+
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
23+
; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]]
24+
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
25+
; P5600: RetRA
26+
%0:_(p0) = COPY $a0
27+
%1:_(p0) = COPY $a1
28+
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
29+
%3:_(<4 x s32>) = G_FSQRT %2
30+
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
31+
RetRA
32+
33+
...
34+
---
35+
name: sqrt_v2f64
36+
alignment: 4
37+
legalized: true
38+
tracksRegLiveness: true
39+
body: |
40+
bb.1.entry:
41+
liveins: $a0, $a1
42+
43+
; P5600-LABEL: name: sqrt_v2f64
44+
; P5600: liveins: $a0, $a1
45+
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
46+
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
47+
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
48+
; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]]
49+
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
50+
; P5600: RetRA
51+
%0:_(p0) = COPY $a0
52+
%1:_(p0) = COPY $a1
53+
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
54+
%3:_(<2 x s64>) = G_FSQRT %2
55+
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
56+
RetRA
57+
58+
...

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