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[AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.
Fixed bugs 48639, 49447, 49448, 49449.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst

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‎llvm/docs/AMDGPU/gfx9_attr.rst

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attr
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===========================
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====
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Interpolation attribute and channel:
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‎llvm/docs/AMDGPU/gfx9_ret.rst renamed to ‎llvm/docs/AMDGPU/gfx9_dst.rst

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dst
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===========================
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===
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This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

‎llvm/docs/AMDGPU/gfx9_hwreg.rst

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hwreg
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===========================
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Bits of a hardware register being accessed.
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‎llvm/docs/AMDGPU/gfx9_imask.rst

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imask
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===========================
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=====
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This operand is a mask which controls indexing mode for operands of subsequent instructions.
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Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.

‎llvm/docs/AMDGPU/gfx9_simm16.rst renamed to ‎llvm/docs/AMDGPU/gfx9_imm16.rst

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.. _amdgpu_synid_gfx9_imm16:
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imm16
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===========================
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

‎llvm/docs/AMDGPU/gfx9_uimm16.rst renamed to ‎llvm/docs/AMDGPU/gfx9_imm16_1.rst

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imm16
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===========================
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

‎llvm/docs/AMDGPU/gfx9_bimm16.rst renamed to ‎llvm/docs/AMDGPU/gfx9_imm16_2.rst

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imm16
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===========================
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A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

‎llvm/docs/AMDGPU/gfx9_label.rst

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label
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===========================
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=====
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A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
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‎llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst renamed to ‎llvm/docs/AMDGPU/gfx9_m.rst

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m
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===========================
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=
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This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.

‎llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst renamed to ‎llvm/docs/AMDGPU/gfx9_m_1.rst

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m
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===========================
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=
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This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.

‎llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst

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‎llvm/docs/AMDGPU/gfx9_msg.rst

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msg
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A 16-bit message code. The bits of this operand have the following meaning:
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s_sendmsg sendmsg(msg, op, stream)
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s_sendmsg sendmsg(2, GS_OP_CUT)
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‎llvm/docs/AMDGPU/gfx9_opt.rst

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opt
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This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.

‎llvm/docs/AMDGPU/gfx9_param.rst

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param
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Interpolation parameter to read:
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‎llvm/docs/AMDGPU/gfx9_perm_smem.rst renamed to ‎llvm/docs/AMDGPU/gfx9_probe.rst

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imm3
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===========================
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probe
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=====
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A bit mask which indicates request permissions.
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‎llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst renamed to ‎llvm/docs/AMDGPU/gfx9_saddr.rst

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An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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See :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` for description of available addressing modes.
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See :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` for description of available addressing modes.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`

‎llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst renamed to ‎llvm/docs/AMDGPU/gfx9_saddr_1.rst

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An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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Either this operand or :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
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Either this operand or :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`

‎llvm/docs/AMDGPU/gfx9_base_smem_addr.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sbase.rst

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A 64-bit base address for scalar memory operations.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_base_smem_buf.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sbase_1.rst

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A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
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‎llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sbase_2.rst

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This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata.rst

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Input data for an atomic instruction.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata_1.rst

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Input data for an atomic instruction.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata_2.rst

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Input data for an atomic instruction.
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‎llvm/docs/AMDGPU/gfx9_sdata32_0.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata_3.rst

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Instruction input.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_sdata64_0.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata_4.rst

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Instruction input.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx9_sdata128_0.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdata_5.rst

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Instruction input.
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‎llvm/docs/AMDGPU/gfx9_sdst32_0.rst renamed to ‎llvm/docs/AMDGPU/gfx9_sdst.rst

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Instruction output.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

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