@@ -589,7 +589,7 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
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DESC, ADDITIONAL_OPERATION) \
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do { \
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if (FEATURE_CHECKS) { \
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- LLVM_DEBUG (dbgs () << " Trying " DESC " :\n " ); \
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+ LLVM_DEBUG (dbgs () << " Trying " << DESC << " table :\n " ); \
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DecodeStatus Result = \
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decodeInstruction (DECODER_TABLE, MI, Insn, Address, this , STI); \
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if (Result != MCDisassembler::Fail) { \
@@ -622,106 +622,96 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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TRY_TO_DECODE (STI.hasFeature (RISCV::FeatureStdExtZdinx) &&
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!STI.hasFeature (RISCV::Feature64Bit),
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DecoderTableRV32Zdinx32,
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- " RV32Zdinx table (Double in Integer and rv32)" );
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+ " RV32Zdinx (Double in Integer and rv32)" );
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TRY_TO_DECODE (STI.hasFeature (RISCV::FeatureStdExtZacas) &&
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!STI.hasFeature (RISCV::Feature64Bit),
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DecoderTableRV32Zacas32,
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- " RV32Zacas table (Compare-And-Swap and rv32)" );
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+ " RV32Zacas (Compare-And-Swap and rv32)" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
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- " RVZfinx table (Float in Integer)" );
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+ " RVZfinx (Float in Integer)" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXVentanaCondOps,
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- DecoderTableXVentana32, " Ventana custom opcode table " );
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+ DecoderTableXVentana32, " XVentanaCondOps " );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
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- " XTHeadBa custom opcode table " );
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+ " XTHeadBa" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
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- " XTHeadBb custom opcode table " );
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+ " XTHeadBb" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
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- " XTHeadBs custom opcode table " );
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+ " XTHeadBs" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadCondMov,
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- DecoderTableXTHeadCondMov32,
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- " XTHeadCondMov custom opcode table" );
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+ DecoderTableXTHeadCondMov32, " XTHeadCondMov" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
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- " XTHeadCmo custom opcode table " );
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+ " XTHeadCmo" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadFMemIdx,
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- DecoderTableXTHeadFMemIdx32,
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- " XTHeadFMemIdx custom opcode table" );
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+ DecoderTableXTHeadFMemIdx32, " XTHeadFMemIdx" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
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- " XTHeadMac custom opcode table " );
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+ " XTHeadMac" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMemIdx,
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- DecoderTableXTHeadMemIdx32,
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- " XTHeadMemIdx custom opcode table" );
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+ DecoderTableXTHeadMemIdx32, " XTHeadMemIdx" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMemPair,
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- DecoderTableXTHeadMemPair32,
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- " XTHeadMemPair custom opcode table" );
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+ DecoderTableXTHeadMemPair32, " XTHeadMemPair" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadSync,
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- DecoderTableXTHeadSync32,
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- " XTHeadSync custom opcode table" );
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+ DecoderTableXTHeadSync32, " XTHeadSync" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadVdot,
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- DecoderTableXTHeadVdot32,
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- " XTHeadVdot custom opcode table" );
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+ DecoderTableXTHeadVdot32, " XTHeadVdot" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
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- " SiFive VCIX custom opcode table " );
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+ " SiFive VCIX" );
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TRY_TO_DECODE_FEATURE (
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RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
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- " SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table " );
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+ " SiFive Matrix Multiplication (2x8 and 8x2) Instruction" );
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TRY_TO_DECODE_FEATURE (
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RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
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- " SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table " );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
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- " SiFive Matrix Multiplication Instruction opcode table " );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
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- " SiFive FP32-to-int8 Ranged Clip Instructions opcode table " );
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+ " SiFive Matrix Multiplication (4x8 and 8x4) Instruction" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvfwmaccqqq,
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+ DecoderTableXSfvfwmaccqqq32,
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+ " SiFive Matrix Multiplication Instruction" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvfnrclipxfqf,
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+ DecoderTableXSfvfnrclipxfqf32,
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+ " SiFive FP32-to-int8 Ranged Clip Instructions" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSiFivecdiscarddlone,
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DecoderTableXSiFivecdiscarddlone32,
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- " SiFive sf.cdiscard.d.l1 custom opcode table " );
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+ " SiFive sf.cdiscard.d.l1" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSiFivecflushdlone,
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DecoderTableXSiFivecflushdlone32,
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- " SiFive sf.cflush.d.l1 custom opcode table " );
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+ " SiFive sf.cflush.d.l1" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
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- " SiFive sf.cease custom opcode table " );
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+ " SiFive sf.cease" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXMIPSLSP, DecoderTableXmipslsp32,
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- " MIPS mips.lsp custom opcode table " );
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+ " MIPS mips.lsp" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXMIPSCMove,
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- DecoderTableXmipscmove32,
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- " MIPS mips.ccmov custom opcode table" );
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+ DecoderTableXmipscmove32, " MIPS mips.ccmov" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVbitmanip,
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- DecoderTableXCVbitmanip32,
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- " CORE-V Bit Manipulation custom opcode table" );
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+ DecoderTableXCVbitmanip32, " CORE-V Bit Manipulation" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
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- " CORE-V Event load custom opcode table " );
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+ " CORE-V Event load" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
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- " CORE-V MAC custom opcode table " );
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+ " CORE-V MAC" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
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- " CORE-V MEM custom opcode table " );
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+ " CORE-V MEM" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
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- " CORE-V ALU custom opcode table " );
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+ " CORE-V ALU" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
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- " CORE-V SIMD extensions custom opcode table " );
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+ " CORE-V SIMD extensions" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
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- " CORE-V Immediate Branching custom opcode table " );
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+ " CORE-V Immediate Branching" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
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- " Qualcomm uC CSR custom opcode table " );
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+ " Qualcomm uC CSR" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
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- " Qualcomm uC Scaled Load Store custom opcode table " );
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+ " Qualcomm uC Scaled Load Store" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
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- " Qualcomm uC Arithmetic custom opcode table " );
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+ " Qualcomm uC Arithmetic" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
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- " Qualcomm uC Conditional Select custom opcode table " );
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+ " Qualcomm uC Conditional Select" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
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- " Qualcomm uC Load Store Multiple custom opcode table" );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
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- " Qualcomm uC Load-Store Address Calculation custom opcode table" );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
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- " Qualcomm uC Conditional Load Immediate custom opcode table" );
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+ " Qualcomm uC Load Store Multiple" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
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+ " Qualcomm uC Load-Store Address Calculation" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
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+ " Qualcomm uC Conditional Load Immediate" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
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- " Qualcomm uC Conditional Move custom opcode table " );
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+ " Qualcomm uC Conditional Move" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
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- " Qualcomm uC Interrupts custom opcode table " );
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- TRY_TO_DECODE (true , DecoderTable32, " RISCV32 table " );
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+ " Qualcomm uC Interrupts" );
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+ TRY_TO_DECODE (true , DecoderTable32, " RISCV32" );
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return MCDisassembler::Fail;
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}
@@ -739,27 +729,23 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
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uint32_t Insn = support::endian::read16le (Bytes.data ());
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TRY_TO_DECODE_AND_ADD_SP (!STI.hasFeature (RISCV::Feature64Bit),
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DecoderTableRISCV32Only_16,
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- " RISCV32Only_16 table (16-bit Instruction)" );
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+ " RISCV32Only_16 (16-bit Instruction)" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
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- " RVZicfiss table (Shadow Stack)" );
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+ " RVZicfiss (Shadow Stack)" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
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- " Zcmt table (16-bit Table Jump Instructions)" );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
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- " Zcmp table (16-bit Push/Pop & Double Move Instructions)" );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
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- " Qualcomm uC Load-Store Address Calculation custom 16bit opcode table" );
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
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- " Qualcomm uC Conditional Move custom 16bit opcode table" );
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+ " Zcmt (16-bit Table Jump Instructions)" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
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+ " Zcmp (16-bit Push/Pop & Double Move Instructions)" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
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+ " Qualcomm uC Load-Store Address Calculation 16bit" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
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+ " Qualcomm uC Conditional Move 16bit" );
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TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciint, DecoderTableXqciint16,
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- " Qualcomm uC Interrupts custom 16bit opcode table " );
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+ " Qualcomm uC Interrupts 16bit" );
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TRY_TO_DECODE_AND_ADD_SP (STI.hasFeature (RISCV::FeatureVendorXwchc),
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- DecoderTableXwchc16,
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- " WCH QingKe XW custom opcode table" );
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+ DecoderTableXwchc16, " WCH QingKe XW" );
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TRY_TO_DECODE_AND_ADD_SP (true , DecoderTable16,
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- " RISCV_C table (16-bit Instruction)" );
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+ " RISCV_C (16-bit Instruction)" );
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return MCDisassembler::Fail;
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}
@@ -778,9 +764,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
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for (size_t i = Size; i-- != 0 ;) {
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Insn += (static_cast <uint64_t >(Bytes[i]) << 8 * i);
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}
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- TRY_TO_DECODE_FEATURE (
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- RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
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- " Qualcomm uC Large Offset Load Store custom 48bit opcode table" );
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+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
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+ " Qualcomm uC Large Offset Load Store 48bit" );
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return MCDisassembler::Fail;
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}
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