Skip to content

Commit 474e37c

Browse files
eopXDeopXD
committed
[1/8][RISCV] Add rounding mode control variant for vfsub, vfrsub
Depends on D152996. This patch-set aims to add a variant for the RVV floating-point intrinsics that controls the rounding mode (`frm`). The rounding mode variant appends `_rm` before the policy suffix to distinguish from those without them. Specification PR: riscv-non-isa/rvv-intrinsic-doc#226 This is the 1st patch of the patch-set. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154628
1 parent 7648207 commit 474e37c

File tree

19 files changed

+6229
-795
lines changed

19 files changed

+6229
-795
lines changed

‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -235,6 +235,10 @@ multiclass RVVFloatingBinVFBuiltinSet
235235
: RVVOutOp1BuiltinSet<NAME, "xfd",
236236
[["vf", "v", "vve"]]>;
237237

238+
multiclass RVVFloatingBinVFBuiltinSetRoundingMode
239+
: RVVOutOp1BuiltinSet<NAME, "xfd",
240+
[["vf", "v", "vveu"]]>;
241+
238242
multiclass RVVFloatingMaskOutBuiltinSet
239243
: RVVOp0Op1BuiltinSet<NAME, "xfd",
240244
[["vv", "vm", "mvv"],
@@ -1876,7 +1880,6 @@ enum __RISCV_FRM {
18761880
}] in def frm_enum : RVVHeader;
18771881

18781882
let UnMaskedPolicyScheme = HasPassthruOperand in {
1879-
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
18801883
let ManualCodegen = [{
18811884
{
18821885
// LLVM intrinsic
@@ -1923,12 +1926,16 @@ let ManualCodegen = [{
19231926
}
19241927
}] in {
19251928
let HasFRMRoundModeOp = true in {
1929+
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
19261930
defm vfadd : RVVFloatingBinBuiltinSetRoundingMode;
1931+
defm vfsub : RVVFloatingBinBuiltinSetRoundingMode;
1932+
defm vfrsub : RVVFloatingBinVFBuiltinSetRoundingMode;
19271933
}
1934+
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
19281935
defm vfadd : RVVFloatingBinBuiltinSet;
1936+
defm vfsub : RVVFloatingBinBuiltinSet;
1937+
defm vfrsub : RVVFloatingBinVFBuiltinSet;
19291938
}
1930-
defm vfsub : RVVFloatingBinBuiltinSet;
1931-
defm vfrsub : RVVFloatingBinVFBuiltinSet;
19321939

19331940
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
19341941
// Widening FP add/subtract, 2*SEW = SEW +/- SEW

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4810,18 +4810,36 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
48104810
return SemaBuiltinConstantArgRange(TheCall, 4, 0, 3);
48114811
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:
48124812
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:
4813+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm:
4814+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm:
4815+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:
48134816
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 4);
48144817
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:
48154818
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
4819+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:
4820+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:
4821+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:
48164822
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama:
48174823
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama:
4824+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tama:
4825+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tama:
4826+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tama:
48184827
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4);
48194828
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
48204829
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
4830+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
4831+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:
4832+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:
48214833
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:
48224834
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:
4835+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:
4836+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:
4837+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:
48234838
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
48244839
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
4840+
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
4841+
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:
4842+
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:
48254843
return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4);
48264844
case RISCV::BI__builtin_riscv_ntl_load:
48274845
case RISCV::BI__builtin_riscv_ntl_store:

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c

Lines changed: 330 additions & 30 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c

Lines changed: 660 additions & 60 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c

Lines changed: 330 additions & 30 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c

Lines changed: 660 additions & 60 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c

Lines changed: 660 additions & 60 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c

Lines changed: 1320 additions & 120 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c

Lines changed: 660 additions & 60 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c

Lines changed: 1320 additions & 120 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1322,8 +1322,8 @@ let TargetPrefix = "riscv" in {
13221322
defm vwmaccsu : RISCVTernaryWide;
13231323

13241324
defm vfadd : RISCVBinaryAAXRoundingMode;
1325-
defm vfsub : RISCVBinaryAAX;
1326-
defm vfrsub : RISCVBinaryAAX;
1325+
defm vfsub : RISCVBinaryAAXRoundingMode;
1326+
defm vfrsub : RISCVBinaryAAXRoundingMode;
13271327

13281328
defm vfwadd : RISCVBinaryABX;
13291329
defm vfwsub : RISCVBinaryABX;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2732,6 +2732,20 @@ multiclass VPseudoVALU_VF {
27322732
}
27332733
}
27342734

2735+
multiclass VPseudoVALU_VF_RM {
2736+
foreach f = FPList in {
2737+
foreach m = f.MxList in {
2738+
defvar mx = m.MX;
2739+
defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
2740+
defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
2741+
defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
2742+
2743+
defm "" : VPseudoBinaryV_VF_RM<m, f>,
2744+
Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
2745+
}
2746+
}
2747+
}
2748+
27352749
multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
27362750
foreach m = MxList in {
27372751
defvar mx = m.MX;
@@ -5711,11 +5725,8 @@ let Predicates = [HasVInstructionsAnyF] in {
57115725
let mayRaiseFPException = true,
57125726
hasPostISelHook = 1 in {
57135727
defm PseudoVFADD : VPseudoVALU_VV_VF_RM;
5714-
}
5715-
5716-
let Uses = [FRM], mayRaiseFPException = true in {
5717-
defm PseudoVFSUB : VPseudoVALU_VV_VF;
5718-
defm PseudoVFRSUB : VPseudoVALU_VF;
5728+
defm PseudoVFSUB : VPseudoVALU_VV_VF_RM;
5729+
defm PseudoVFRSUB : VPseudoVALU_VF_RM;
57195730
}
57205731

57215732
//===----------------------------------------------------------------------===//
@@ -6374,8 +6385,9 @@ defm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclip", "PseudoVNCLIP",
63746385
//===----------------------------------------------------------------------===//
63756386
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD",
63766387
AllFloatVectors>;
6377-
defm : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>;
6378-
defm : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
6388+
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB",
6389+
AllFloatVectors>;
6390+
defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
63796391

63806392
//===----------------------------------------------------------------------===//
63816393
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,25 @@ multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_nam
262262
fvti.AVL, fvti.Log2SEW, TA_MA)>;
263263
}
264264

265+
multiclass VPatBinaryFPSDNode_R_VF_RM<SDPatternOperator vop, string instruction_name,
266+
bit isSEWAware = 0> {
267+
foreach fvti = AllFloatVectors in
268+
let Predicates = GetVTypePredicates<fvti>.Predicates in
269+
def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
270+
(fvti.Vector fvti.RegClass:$rs1))),
271+
(!cast<Instruction>(
272+
!if(isSEWAware,
273+
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
274+
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX))
275+
(fvti.Vector (IMPLICIT_DEF)),
276+
fvti.RegClass:$rs1,
277+
(fvti.Scalar fvti.ScalarRegClass:$rs2),
278+
// Value to indicate no rounding mode change in
279+
// RISCVInsertReadWriteCSR
280+
FRM_DYN,
281+
fvti.AVL, fvti.Log2SEW, TA_MA)>;
282+
}
283+
265284
multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
266285
CondCode cc> {
267286
foreach vti = AllIntegerVectors in {
@@ -1036,8 +1055,8 @@ foreach mti = AllMasks in {
10361055

10371056
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
10381057
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fadd, "PseudoVFADD">;
1039-
defm : VPatBinaryFPSDNode_VV_VF<any_fsub, "PseudoVFSUB">;
1040-
defm : VPatBinaryFPSDNode_R_VF<any_fsub, "PseudoVFRSUB">;
1058+
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fsub, "PseudoVFSUB">;
1059+
defm : VPatBinaryFPSDNode_R_VF_RM<any_fsub, "PseudoVFRSUB">;
10411060

10421061
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
10431062
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -898,6 +898,29 @@ multiclass VPatBinaryFPVL_R_VF<SDPatternOperator vop, string instruction_name,
898898
}
899899
}
900900

901+
multiclass VPatBinaryFPVL_R_VF_RM<SDPatternOperator vop, string instruction_name,
902+
bit isSEWAware = 0> {
903+
foreach fvti = AllFloatVectors in {
904+
let Predicates = GetVTypePredicates<fvti>.Predicates in
905+
def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
906+
fvti.RegClass:$rs1,
907+
(fvti.Vector fvti.RegClass:$merge),
908+
(fvti.Mask V0),
909+
VLOpFrag)),
910+
(!cast<Instruction>(
911+
!if(isSEWAware,
912+
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",
913+
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK"))
914+
fvti.RegClass:$merge,
915+
fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
916+
(fvti.Mask V0),
917+
// Value to indicate no rounding mode change in
918+
// RISCVInsertReadWriteCSR
919+
FRM_DYN,
920+
GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
921+
}
922+
}
923+
901924
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
902925
CondCode cc> {
903926
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
@@ -1915,8 +1938,8 @@ defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">;
19151938

19161939
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
19171940
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD">;
1918-
defm : VPatBinaryFPVL_VV_VF<any_riscv_fsub_vl, "PseudoVFSUB">;
1919-
defm : VPatBinaryFPVL_R_VF<any_riscv_fsub_vl, "PseudoVFRSUB">;
1941+
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB">;
1942+
defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB">;
19201943

19211944
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
19221945
defm : VPatBinaryFPWVL_VV_VF_WV_WF<riscv_vfwadd_vl, riscv_vfwadd_w_vl, "PseudoVFWADD">;

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,13 +53,13 @@ define <vscale x 2 x float> @vpmerge_vfsub(<vscale x 2 x float> %passthru, <vsca
5353
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
5454
; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t
5555
; CHECK-NEXT: ret
56-
%a = call <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %x, <vscale x 2 x float> %y, <vscale x 2 x i1> %m, i64 %vl, i64 1)
56+
%a = call <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %x, <vscale x 2 x float> %y, <vscale x 2 x i1> %m, i64 7, i64 %vl, i64 1)
5757
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
5858
%mask = shufflevector <vscale x 2 x i1> %splat, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
5959
%b = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x i1> %mask, i64 %vl)
6060
ret <vscale x 2 x float> %b
6161
}
62-
declare <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64)
62+
declare <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64, i64)
6363

6464
define <vscale x 2 x i32> @vpmerge_vwadd(<vscale x 2 x i32> %passthru, <vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i64 %vl) {
6565
; CHECK-LABEL: vpmerge_vwadd:

‎llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -482,7 +482,7 @@ declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16(
482482
<vscale x 1 x half>,
483483
<vscale x 1 x half>,
484484
half,
485-
iXLen);
485+
iXLen, iXLen);
486486

487487
define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, iXLen %3) nounwind {
488488
; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16:
@@ -495,7 +495,7 @@ entry:
495495
<vscale x 1 x half> %0,
496496
<vscale x 1 x half> %1,
497497
half %2,
498-
iXLen %3)
498+
iXLen 7, iXLen %3)
499499

500500
ret <vscale x 1 x half> %a
501501
}
@@ -681,7 +681,7 @@ declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16(
681681
<vscale x 1 x half>,
682682
<vscale x 1 x half>,
683683
<vscale x 1 x half>,
684-
iXLen);
684+
iXLen, iXLen);
685685

686686
define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
687687
; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16:
@@ -694,7 +694,7 @@ entry:
694694
<vscale x 1 x half> %0,
695695
<vscale x 1 x half> %1,
696696
<vscale x 1 x half> %2,
697-
iXLen %3)
697+
iXLen 7, iXLen %3)
698698

699699
ret <vscale x 1 x half> %a
700700
}

0 commit comments

Comments
 (0)