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[RISCV][GISel] Support G_FMA/NEG/ABS/SQRT/MAXNUM/MINNUM for F and D extension.
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5 files changed

+814
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lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
190190

191191
// FP Operations
192192

193-
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
193+
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FNEG,
194+
G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
194195
.legalIf([=, &ST](const LegalityQuery &Query) -> bool {
195196
return (ST.hasStdExtF() && typeIs(0, s32)(Query)) ||
196197
(ST.hasStdExtD() && typeIs(0, s64)(Query));

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -178,13 +178,32 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
178178
case TargetOpcode::G_FADD:
179179
case TargetOpcode::G_FSUB:
180180
case TargetOpcode::G_FMUL:
181-
case TargetOpcode::G_FDIV: {
181+
case TargetOpcode::G_FDIV:
182+
case TargetOpcode::G_FNEG:
183+
case TargetOpcode::G_FABS:
184+
case TargetOpcode::G_FSQRT:
185+
case TargetOpcode::G_FMAXNUM:
186+
case TargetOpcode::G_FMINNUM: {
182187
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
183188
OperandsMapping = Ty.getSizeInBits() == 64
184189
? &RISCV::ValueMappings[RISCV::FPR64Idx]
185190
: &RISCV::ValueMappings[RISCV::FPR32Idx];
186191
break;
187192
}
193+
case TargetOpcode::G_FMA: {
194+
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
195+
OperandsMapping =
196+
Ty.getSizeInBits() == 64
197+
? getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR64Idx],
198+
&RISCV::ValueMappings[RISCV::FPR64Idx],
199+
&RISCV::ValueMappings[RISCV::FPR64Idx],
200+
&RISCV::ValueMappings[RISCV::FPR64Idx]})
201+
: getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR32Idx],
202+
&RISCV::ValueMappings[RISCV::FPR32Idx],
203+
&RISCV::ValueMappings[RISCV::FPR32Idx],
204+
&RISCV::ValueMappings[RISCV::FPR32Idx]});
205+
break;
206+
}
188207
default:
189208
return getInvalidInstructionMapping();
190209
}

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir

Lines changed: 280 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,98 @@ body: |
9999
$f10_f = COPY %2(s32)
100100
PseudoRET implicit $f10_f
101101
102+
...
103+
---
104+
name: fma_f32
105+
legalized: true
106+
regBankSelected: true
107+
tracksRegLiveness: true
108+
body: |
109+
bb.0:
110+
liveins: $f10_f, $f11_f, $f12_f
111+
112+
; CHECK-LABEL: name: fma_f32
113+
; CHECK: liveins: $f10_f, $f11_f, $f12_f
114+
; CHECK-NEXT: {{ $}}
115+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
116+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
117+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f12_f
118+
; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nofpexcept FMADD_S [[COPY]], [[COPY1]], [[COPY2]], 7
119+
; CHECK-NEXT: $f10_f = COPY [[FMADD_S]]
120+
; CHECK-NEXT: PseudoRET implicit $f10_f
121+
%0:fprb(s32) = COPY $f10_f
122+
%1:fprb(s32) = COPY $f11_f
123+
%2:fprb(s32) = COPY $f12_f
124+
%3:fprb(s32) = G_FMA %0, %1, %2
125+
$f10_f = COPY %3(s32)
126+
PseudoRET implicit $f10_f
127+
128+
...
129+
---
130+
name: fneg_f32
131+
legalized: true
132+
regBankSelected: true
133+
tracksRegLiveness: true
134+
body: |
135+
bb.0:
136+
liveins: $f10_f, $f11_f, $f12_f
137+
138+
; CHECK-LABEL: name: fneg_f32
139+
; CHECK: liveins: $f10_f, $f11_f, $f12_f
140+
; CHECK-NEXT: {{ $}}
141+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
142+
; CHECK-NEXT: [[FSGNJN_S:%[0-9]+]]:fpr32 = FSGNJN_S [[COPY]], [[COPY]]
143+
; CHECK-NEXT: $f10_f = COPY [[FSGNJN_S]]
144+
; CHECK-NEXT: PseudoRET implicit $f10_f
145+
%0:fprb(s32) = COPY $f10_f
146+
%1:fprb(s32) = G_FNEG %0
147+
$f10_f = COPY %1(s32)
148+
PseudoRET implicit $f10_f
149+
150+
...
151+
---
152+
name: fabs_f32
153+
legalized: true
154+
regBankSelected: true
155+
tracksRegLiveness: true
156+
body: |
157+
bb.0:
158+
liveins: $f10_f, $f11_f, $f12_f
159+
160+
; CHECK-LABEL: name: fabs_f32
161+
; CHECK: liveins: $f10_f, $f11_f, $f12_f
162+
; CHECK-NEXT: {{ $}}
163+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
164+
; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[COPY]], [[COPY]]
165+
; CHECK-NEXT: $f10_f = COPY [[FSGNJX_S]]
166+
; CHECK-NEXT: PseudoRET implicit $f10_f
167+
%0:fprb(s32) = COPY $f10_f
168+
%1:fprb(s32) = G_FABS %0
169+
$f10_f = COPY %1(s32)
170+
PseudoRET implicit $f10_f
171+
172+
...
173+
---
174+
name: fsqrt_f32
175+
legalized: true
176+
regBankSelected: true
177+
tracksRegLiveness: true
178+
body: |
179+
bb.0:
180+
liveins: $f10_f, $f11_f, $f12_f
181+
182+
; CHECK-LABEL: name: fsqrt_f32
183+
; CHECK: liveins: $f10_f, $f11_f, $f12_f
184+
; CHECK-NEXT: {{ $}}
185+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
186+
; CHECK-NEXT: [[FSQRT_S:%[0-9]+]]:fpr32 = nofpexcept FSQRT_S [[COPY]], 7
187+
; CHECK-NEXT: $f10_f = COPY [[FSQRT_S]]
188+
; CHECK-NEXT: PseudoRET implicit $f10_f
189+
%0:fprb(s32) = COPY $f10_f
190+
%1:fprb(s32) = G_FSQRT %0
191+
$f10_f = COPY %1(s32)
192+
PseudoRET implicit $f10_f
193+
102194
...
103195
---
104196
name: fadd_f64
@@ -123,6 +215,54 @@ body: |
123215
$f10_d = COPY %2(s64)
124216
PseudoRET implicit $f10_d
125217
218+
...
219+
---
220+
name: fmaxnum_f32
221+
legalized: true
222+
regBankSelected: true
223+
tracksRegLiveness: true
224+
body: |
225+
bb.0:
226+
liveins: $f10_f, $f11_f
227+
228+
; CHECK-LABEL: name: fmaxnum_f32
229+
; CHECK: liveins: $f10_f, $f11_f
230+
; CHECK-NEXT: {{ $}}
231+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
232+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
233+
; CHECK-NEXT: [[FMAX_S:%[0-9]+]]:fpr32 = nofpexcept FMAX_S [[COPY]], [[COPY1]]
234+
; CHECK-NEXT: $f10_f = COPY [[FMAX_S]]
235+
; CHECK-NEXT: PseudoRET implicit $f10_f
236+
%0:fprb(s32) = COPY $f10_f
237+
%1:fprb(s32) = COPY $f11_f
238+
%2:fprb(s32) = G_FMAXNUM %0, %1
239+
$f10_f = COPY %2(s32)
240+
PseudoRET implicit $f10_f
241+
242+
...
243+
---
244+
name: fminnum_f32
245+
legalized: true
246+
regBankSelected: true
247+
tracksRegLiveness: true
248+
body: |
249+
bb.0:
250+
liveins: $f10_f, $f11_f
251+
252+
; CHECK-LABEL: name: fminnum_f32
253+
; CHECK: liveins: $f10_f, $f11_f
254+
; CHECK-NEXT: {{ $}}
255+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
256+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
257+
; CHECK-NEXT: [[FMIN_S:%[0-9]+]]:fpr32 = nofpexcept FMIN_S [[COPY]], [[COPY1]]
258+
; CHECK-NEXT: $f10_f = COPY [[FMIN_S]]
259+
; CHECK-NEXT: PseudoRET implicit $f10_f
260+
%0:fprb(s32) = COPY $f10_f
261+
%1:fprb(s32) = COPY $f11_f
262+
%2:fprb(s32) = G_FMINNUM %0, %1
263+
$f10_f = COPY %2(s32)
264+
PseudoRET implicit $f10_f
265+
126266
...
127267
---
128268
name: fsub_f64
@@ -196,3 +336,143 @@ body: |
196336
PseudoRET implicit $f10_d
197337
198338
...
339+
---
340+
name: fma_f64
341+
legalized: true
342+
regBankSelected: true
343+
tracksRegLiveness: true
344+
body: |
345+
bb.0:
346+
liveins: $f10_d, $f11_d, $f12_d
347+
348+
; CHECK-LABEL: name: fma_f64
349+
; CHECK: liveins: $f10_d, $f11_d, $f12_d
350+
; CHECK-NEXT: {{ $}}
351+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
352+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
353+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f12_d
354+
; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = nofpexcept FMADD_D [[COPY]], [[COPY1]], [[COPY2]], 7
355+
; CHECK-NEXT: $f10_d = COPY [[FMADD_D]]
356+
; CHECK-NEXT: PseudoRET implicit $f10_d
357+
%0:fprb(s64) = COPY $f10_d
358+
%1:fprb(s64) = COPY $f11_d
359+
%2:fprb(s64) = COPY $f12_d
360+
%3:fprb(s64) = G_FMA %0, %1, %2
361+
$f10_d = COPY %3(s64)
362+
PseudoRET implicit $f10_d
363+
364+
...
365+
---
366+
name: fneg_f64
367+
legalized: true
368+
regBankSelected: true
369+
tracksRegLiveness: true
370+
body: |
371+
bb.0:
372+
liveins: $f10_d
373+
374+
; CHECK-LABEL: name: fneg_f64
375+
; CHECK: liveins: $f10_d
376+
; CHECK-NEXT: {{ $}}
377+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
378+
; CHECK-NEXT: [[FSGNJN_D:%[0-9]+]]:fpr64 = FSGNJN_D [[COPY]], [[COPY]]
379+
; CHECK-NEXT: $f10_d = COPY [[FSGNJN_D]]
380+
; CHECK-NEXT: PseudoRET implicit $f10_d
381+
%0:fprb(s64) = COPY $f10_d
382+
%1:fprb(s64) = G_FNEG %0
383+
$f10_d = COPY %1(s64)
384+
PseudoRET implicit $f10_d
385+
386+
...
387+
---
388+
name: fabs_f64
389+
legalized: true
390+
regBankSelected: true
391+
tracksRegLiveness: true
392+
body: |
393+
bb.0:
394+
liveins: $f10_d
395+
396+
; CHECK-LABEL: name: fabs_f64
397+
; CHECK: liveins: $f10_d
398+
; CHECK-NEXT: {{ $}}
399+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
400+
; CHECK-NEXT: [[FSGNJX_D:%[0-9]+]]:fpr64 = FSGNJX_D [[COPY]], [[COPY]]
401+
; CHECK-NEXT: $f10_d = COPY [[FSGNJX_D]]
402+
; CHECK-NEXT: PseudoRET implicit $f10_d
403+
%0:fprb(s64) = COPY $f10_d
404+
%1:fprb(s64) = G_FABS %0
405+
$f10_d = COPY %1(s64)
406+
PseudoRET implicit $f10_d
407+
408+
...
409+
---
410+
name: fsqrt_f64
411+
legalized: true
412+
regBankSelected: true
413+
tracksRegLiveness: true
414+
body: |
415+
bb.0:
416+
liveins: $f10_d
417+
418+
; CHECK-LABEL: name: fsqrt_f64
419+
; CHECK: liveins: $f10_d
420+
; CHECK-NEXT: {{ $}}
421+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
422+
; CHECK-NEXT: [[FSQRT_D:%[0-9]+]]:fpr64 = nofpexcept FSQRT_D [[COPY]], 7
423+
; CHECK-NEXT: $f10_d = COPY [[FSQRT_D]]
424+
; CHECK-NEXT: PseudoRET implicit $f10_d
425+
%0:fprb(s64) = COPY $f10_d
426+
%1:fprb(s64) = G_FSQRT %0
427+
$f10_d = COPY %1(s64)
428+
PseudoRET implicit $f10_d
429+
430+
...
431+
---
432+
name: fmaxnum_f64
433+
legalized: true
434+
regBankSelected: true
435+
tracksRegLiveness: true
436+
body: |
437+
bb.0:
438+
liveins: $f10_d, $f11_d
439+
440+
; CHECK-LABEL: name: fmaxnum_f64
441+
; CHECK: liveins: $f10_d, $f11_d
442+
; CHECK-NEXT: {{ $}}
443+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
444+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
445+
; CHECK-NEXT: [[FMAX_D:%[0-9]+]]:fpr64 = nofpexcept FMAX_D [[COPY]], [[COPY1]]
446+
; CHECK-NEXT: $f10_d = COPY [[FMAX_D]]
447+
; CHECK-NEXT: PseudoRET implicit $f10_d
448+
%0:fprb(s64) = COPY $f10_d
449+
%1:fprb(s64) = COPY $f11_d
450+
%2:fprb(s64) = G_FMAXNUM %0, %1
451+
$f10_d = COPY %2(s64)
452+
PseudoRET implicit $f10_d
453+
454+
...
455+
---
456+
name: fminnum_f64
457+
legalized: true
458+
regBankSelected: true
459+
tracksRegLiveness: true
460+
body: |
461+
bb.0:
462+
liveins: $f10_d, $f11_d
463+
464+
; CHECK-LABEL: name: fminnum_f64
465+
; CHECK: liveins: $f10_d, $f11_d
466+
; CHECK-NEXT: {{ $}}
467+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
468+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
469+
; CHECK-NEXT: [[FMIN_D:%[0-9]+]]:fpr64 = nofpexcept FMIN_D [[COPY]], [[COPY1]]
470+
; CHECK-NEXT: $f10_d = COPY [[FMIN_D]]
471+
; CHECK-NEXT: PseudoRET implicit $f10_d
472+
%0:fprb(s64) = COPY $f10_d
473+
%1:fprb(s64) = COPY $f11_d
474+
%2:fprb(s64) = G_FMINNUM %0, %1
475+
$f10_d = COPY %2(s64)
476+
PseudoRET implicit $f10_d
477+
478+
...

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