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[RISCV] Optimize immediate materialisation with SH*ADD
Use SH1ADD/SH2ADD/SH3ADD along with LUI+ADDI to compose int32*3, int32*5 and int32*9. Reviewed By: craig.topper, luismarques Differential Revision: https://reviews.llvm.org/D111484
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6 files changed

+99
-24
lines changed

6 files changed

+99
-24
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2269,6 +2269,11 @@ void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
22692269
.addReg(DestReg)
22702270
.addReg(SrcReg)
22712271
.addReg(RISCV::X0));
2272+
} else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
2273+
Inst.Opc == RISCV::SH3ADD) {
2274+
emitToStreamer(
2275+
Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
2276+
SrcReg));
22722277
} else {
22732278
emitToStreamer(
22742279
Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,33 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
250250
}
251251
}
252252

253+
// Perform optimization with SH*ADD in the Zba extension.
254+
if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
255+
assert(ActiveFeatures[RISCV::Feature64Bit] &&
256+
"Expected RV32 to only need 2 instructions");
257+
int64_t Div = 0;
258+
unsigned Opc = 0;
259+
RISCVMatInt::InstSeq TmpSeq;
260+
// Select the opcode and divisor.
261+
if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
262+
Div = 3;
263+
Opc = RISCV::SH1ADD;
264+
} else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
265+
Div = 5;
266+
Opc = RISCV::SH2ADD;
267+
} else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
268+
Div = 9;
269+
Opc = RISCV::SH3ADD;
270+
}
271+
// Build the new instruction sequence.
272+
if (Div > 0) {
273+
generateInstSeqImpl(Val / Div, ActiveFeatures, TmpSeq);
274+
TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
275+
if (TmpSeq.size() < Res.size())
276+
Res = TmpSeq;
277+
}
278+
}
279+
253280
return Res;
254281
}
255282

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,9 @@ static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
140140
else if (Inst.Opc == RISCV::ADDUW)
141141
Result = CurDAG->getMachineNode(RISCV::ADDUW, DL, XLenVT, SrcReg,
142142
CurDAG->getRegister(RISCV::X0, XLenVT));
143+
else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
144+
Inst.Opc == RISCV::SH3ADD)
145+
Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SrcReg);
143146
else
144147
Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
145148

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -458,6 +458,12 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
458458
.addReg(SrcReg, RegState::Kill)
459459
.addReg(RISCV::X0)
460460
.setMIFlag(Flag);
461+
} else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
462+
Inst.Opc == RISCV::SH3ADD) {
463+
BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
464+
.addReg(SrcReg, RegState::Kill)
465+
.addReg(SrcReg, RegState::Kill)
466+
.setMIFlag(Flag);
461467
} else {
462468
BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
463469
.addReg(SrcReg, RegState::Kill)

‎llvm/test/CodeGen/RISCV/imm.ll

Lines changed: 18 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -959,10 +959,9 @@ define i64 @imm_neg_5372288229() {
959959
;
960960
; RV64IZBA-LABEL: imm_neg_5372288229:
961961
; RV64IZBA: # %bb.0:
962-
; RV64IZBA-NEXT: lui a0, 1048416
963-
; RV64IZBA-NEXT: addiw a0, a0, -437
964-
; RV64IZBA-NEXT: slli a0, a0, 13
965-
; RV64IZBA-NEXT: addi a0, a0, 795
962+
; RV64IZBA-NEXT: lui a0, 611378
963+
; RV64IZBA-NEXT: addiw a0, a0, 265
964+
; RV64IZBA-NEXT: sh1add a0, a0, a0
966965
; RV64IZBA-NEXT: ret
967966
;
968967
; RV64IZBS-LABEL: imm_neg_5372288229:
@@ -992,10 +991,9 @@ define i64 @imm_8953813715() {
992991
;
993992
; RV64IZBA-LABEL: imm_8953813715:
994993
; RV64IZBA: # %bb.0:
995-
; RV64IZBA-NEXT: lui a0, 267
996-
; RV64IZBA-NEXT: addiw a0, a0, -637
997-
; RV64IZBA-NEXT: slli a0, a0, 13
998-
; RV64IZBA-NEXT: addi a0, a0, -1325
994+
; RV64IZBA-NEXT: lui a0, 437198
995+
; RV64IZBA-NEXT: addiw a0, a0, -265
996+
; RV64IZBA-NEXT: sh2add a0, a0, a0
999997
; RV64IZBA-NEXT: ret
1000998
;
1001999
; RV64IZBS-LABEL: imm_8953813715:
@@ -1025,10 +1023,9 @@ define i64 @imm_neg_8953813715() {
10251023
;
10261024
; RV64IZBA-LABEL: imm_neg_8953813715:
10271025
; RV64IZBA: # %bb.0:
1028-
; RV64IZBA-NEXT: lui a0, 1048309
1029-
; RV64IZBA-NEXT: addiw a0, a0, 637
1030-
; RV64IZBA-NEXT: slli a0, a0, 13
1031-
; RV64IZBA-NEXT: addi a0, a0, 1325
1026+
; RV64IZBA-NEXT: lui a0, 611378
1027+
; RV64IZBA-NEXT: addiw a0, a0, 265
1028+
; RV64IZBA-NEXT: sh2add a0, a0, a0
10321029
; RV64IZBA-NEXT: ret
10331030
;
10341031
; RV64IZBS-LABEL: imm_neg_8953813715:
@@ -1058,10 +1055,9 @@ define i64 @imm_16116864687() {
10581055
;
10591056
; RV64IZBA-LABEL: imm_16116864687:
10601057
; RV64IZBA: # %bb.0:
1061-
; RV64IZBA-NEXT: lui a0, 961
1062-
; RV64IZBA-NEXT: addiw a0, a0, -1475
1063-
; RV64IZBA-NEXT: slli a0, a0, 12
1064-
; RV64IZBA-NEXT: addi a0, a0, 1711
1058+
; RV64IZBA-NEXT: lui a0, 437198
1059+
; RV64IZBA-NEXT: addiw a0, a0, -265
1060+
; RV64IZBA-NEXT: sh3add a0, a0, a0
10651061
; RV64IZBA-NEXT: ret
10661062
;
10671063
; RV64IZBS-LABEL: imm_16116864687:
@@ -1092,10 +1088,9 @@ define i64 @imm_neg_16116864687() {
10921088
;
10931089
; RV64IZBA-LABEL: imm_neg_16116864687:
10941090
; RV64IZBA: # %bb.0:
1095-
; RV64IZBA-NEXT: lui a0, 1047615
1096-
; RV64IZBA-NEXT: addiw a0, a0, 1475
1097-
; RV64IZBA-NEXT: slli a0, a0, 12
1098-
; RV64IZBA-NEXT: addi a0, a0, -1711
1091+
; RV64IZBA-NEXT: lui a0, 611378
1092+
; RV64IZBA-NEXT: addiw a0, a0, 265
1093+
; RV64IZBA-NEXT: sh3add a0, a0, a0
10991094
; RV64IZBA-NEXT: ret
11001095
;
11011096
; RV64IZBS-LABEL: imm_neg_16116864687:
@@ -1447,10 +1442,9 @@ define i64 @imm_neg_2863311530() {
14471442
;
14481443
; RV64IZBA-LABEL: imm_neg_2863311530:
14491444
; RV64IZBA: # %bb.0:
1450-
; RV64IZBA-NEXT: lui a0, 1048405
1451-
; RV64IZBA-NEXT: addiw a0, a0, 1365
1452-
; RV64IZBA-NEXT: slli a0, a0, 12
1453-
; RV64IZBA-NEXT: addi a0, a0, 1366
1445+
; RV64IZBA-NEXT: lui a0, 908766
1446+
; RV64IZBA-NEXT: addiw a0, a0, -546
1447+
; RV64IZBA-NEXT: sh2add a0, a0, a0
14541448
; RV64IZBA-NEXT: ret
14551449
;
14561450
; RV64IZBS-LABEL: imm_neg_2863311530:

‎llvm/test/MC/RISCV/rv64zba-aliases-valid.s

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,3 +46,43 @@ li x5, 0xbbbbb0007bb
4646
# CHECK-S-OBJ: lui t0, 768955
4747
# CHECK-S-OBJ-NEXT: slli.uw t0, t0, 4
4848
li x5, 0xbbbbb0000
49+
50+
# CHECK-S-OBJ-NOALIAS: lui t1, 611378
51+
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
52+
# CHECK-S-OBJ-NOALIAS-NEXT: sh1add t1, t1, t1
53+
# CHECK-S-OBJ: lui t1, 611378
54+
# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
55+
# CHECK-S-OBJ-NEXT: sh1add t1, t1, t1
56+
li x6, -5372288229
57+
58+
# CHECK-S-OBJ-NOALIAS: lui t1, 437198
59+
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -265
60+
# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
61+
# CHECK-S-OBJ: lui t1, 437198
62+
# CHECK-S-OBJ-NEXT: addiw t1, t1, -265
63+
# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
64+
li x6, 8953813715
65+
66+
# CHECK-S-OBJ-NOALIAS: lui t1, 611378
67+
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
68+
# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
69+
# CHECK-S-OBJ: lui t1, 611378
70+
# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
71+
# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
72+
li x6, -8953813715
73+
74+
# CHECK-S-OBJ-NOALIAS: lui t1, 437198
75+
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -265
76+
# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
77+
# CHECK-S-OBJ: lui t1, 437198
78+
# CHECK-S-OBJ-NEXT: addiw t1, t1, -265
79+
# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
80+
li x6, 16116864687
81+
82+
# CHECK-S-OBJ-NOALIAS: lui t1, 611378
83+
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
84+
# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
85+
# CHECK-S-OBJ: lui t1, 611378
86+
# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
87+
# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
88+
li x6, -16116864687

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