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[RISCV] Use HasVInstructions and HasVInstructionsAnyF in more place in TableGen. NFC
Change RISCVSubtarget.hasVInstructionAnyF() to call hasVInstructionsF32 so that any changes to hasVInstructionsF32 are reflected. The files were missed in D112496.
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3 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -367,7 +367,7 @@ multiclass VPatNConvertFP2ISDNode_V<SDNode vop, string instruction_name> {
367367
// Patterns.
368368
//===----------------------------------------------------------------------===//
369369

370-
let Predicates = [HasStdExtV] in {
370+
let Predicates = [HasVInstructions] in {
371371

372372
// 7.4. Vector Unit-Stride Instructions
373373
foreach vti = !listconcat(FractionalGroupIntegerVectors,
@@ -573,9 +573,9 @@ foreach mti = AllMasks in {
573573
VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>;
574574
}
575575

576-
} // Predicates = [HasStdExtV]
576+
} // Predicates = [HasVInstructions]
577577

578-
let Predicates = [HasStdExtV, HasStdExtF] in {
578+
let Predicates = [HasVInstructionsAnyF] in {
579579

580580
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
581581
defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
@@ -757,13 +757,13 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
757757
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
758758
fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
759759
}
760-
} // Predicates = [HasStdExtV, HasStdExtF]
760+
} // Predicates = [HasVInstructionsAnyF]
761761

762762
//===----------------------------------------------------------------------===//
763763
// Vector Splats
764764
//===----------------------------------------------------------------------===//
765765

766-
let Predicates = [HasStdExtV] in {
766+
let Predicates = [HasVInstructions] in {
767767
foreach vti = AllIntegerVectors in {
768768
def : Pat<(vti.Vector (SplatPat GPR:$rs1)),
769769
(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
@@ -772,9 +772,9 @@ foreach vti = AllIntegerVectors in {
772772
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
773773
simm5:$rs1, vti.AVL, vti.Log2SEW)>;
774774
}
775-
} // Predicates = [HasStdExtV]
775+
} // Predicates = [HasVInstructions]
776776

777-
let Predicates = [HasStdExtV, HasStdExtF] in {
777+
let Predicates = [HasVInstructionsAnyF] in {
778778
foreach fvti = AllFloatVectors in {
779779
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
780780
(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
@@ -785,12 +785,12 @@ foreach fvti = AllFloatVectors in {
785785
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
786786
0, fvti.AVL, fvti.Log2SEW)>;
787787
}
788-
} // Predicates = [HasStdExtV, HasStdExtF]
788+
} // Predicates = [HasVInstructionsAnyF]
789789

790790
//===----------------------------------------------------------------------===//
791791
// Vector Element Extracts
792792
//===----------------------------------------------------------------------===//
793-
let Predicates = [HasStdExtV, HasStdExtF] in
793+
let Predicates = [HasVInstructionsAnyF] in
794794
foreach vti = AllFloatVectors in {
795795
defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
796796
vti.ScalarSuffix,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -606,7 +606,7 @@ multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
606606
// Patterns.
607607
//===----------------------------------------------------------------------===//
608608

609-
let Predicates = [HasStdExtV] in {
609+
let Predicates = [HasVInstructions] in {
610610

611611
// 7.4. Vector Unit-Stride Instructions
612612
foreach vti = AllVectors in {
@@ -925,10 +925,10 @@ defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">;
925925
defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">;
926926
defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">;
927927

928-
} // Predicates = [HasStdExtV]
928+
} // Predicates = [HasVInstructions]
929929

930930
// 15.1. Vector Single-Width Integer Reduction Instructions
931-
let Predicates = [HasStdExtV] in {
931+
let Predicates = [HasVInstructions] in {
932932
defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>;
933933
defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>;
934934
defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>;
@@ -937,17 +937,17 @@ defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>;
937937
defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>;
938938
defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>;
939939
defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>;
940-
} // Predicates = [HasStdExtV]
940+
} // Predicates = [HasVInstructions]
941941

942942
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
943-
let Predicates = [HasStdExtV, HasStdExtF] in {
943+
let Predicates = [HasVInstructionsAnyF] in {
944944
defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>;
945945
defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>;
946946
defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>;
947947
defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>;
948-
} // Predicates = [HasStdExtV, HasStdExtF]
948+
} // Predicates = [HasVInstructionsAnyF]
949949

950-
let Predicates = [HasStdExtV, HasStdExtF] in {
950+
let Predicates = [HasVInstructionsAnyF] in {
951951

952952
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
953953
defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">;
@@ -1209,9 +1209,9 @@ foreach fvti = AllFloatVectors in {
12091209
}
12101210
}
12111211

1212-
} // Predicates = [HasStdExtV, HasStdExtF]
1212+
} // Predicates = [HasVInstructionsAnyF]
12131213

1214-
let Predicates = [HasStdExtV] in {
1214+
let Predicates = [HasVInstructions] in {
12151215

12161216
foreach mti = AllMasks in {
12171217
// 16.1 Vector Mask-Register Logical Instructions
@@ -1279,9 +1279,9 @@ foreach mti = AllMasks in {
12791279
VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
12801280
}
12811281

1282-
} // Predicates = [HasStdExtV]
1282+
} // Predicates = [HasVInstructions]
12831283

1284-
let Predicates = [HasStdExtV] in {
1284+
let Predicates = [HasVInstructions] in {
12851285
// 17.1. Integer Scalar Move Instructions
12861286
// 17.4. Vector Register Gather Instruction
12871287
foreach vti = AllIntegerVectors in {
@@ -1361,9 +1361,9 @@ foreach vti = AllIntegerVectors in {
13611361
}
13621362
}
13631363

1364-
} // Predicates = [HasStdExtV]
1364+
} // Predicates = [HasVInstructions]
13651365

1366-
let Predicates = [HasStdExtV, HasStdExtF] in {
1366+
let Predicates = [HasVInstructionsAnyF] in {
13671367

13681368
// 17.2. Floating-Point Scalar Move Instructions
13691369
foreach vti = AllFloatVectors in {
@@ -1443,7 +1443,7 @@ foreach vti = AllFloatVectors in {
14431443
}
14441444
}
14451445

1446-
} // Predicates = [HasStdExtV, HasStdExtF]
1446+
} // Predicates = [HasVInstructionsAnyF]
14471447

14481448
//===----------------------------------------------------------------------===//
14491449
// Miscellaneous RISCVISD SDNodes
@@ -1467,7 +1467,7 @@ def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>;
14671467
def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>;
14681468
def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>;
14691469

1470-
let Predicates = [HasStdExtV] in {
1470+
let Predicates = [HasVInstructions] in {
14711471

14721472
foreach vti = AllIntegerVectors in {
14731473
def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask),
@@ -1520,4 +1520,4 @@ foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in {
15201520
GPR:$vl, vti.Log2SEW)>;
15211521
}
15221522

1523-
} // Predicates = [HasStdExtV]
1523+
} // Predicates = [HasVInstructions]

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -138,8 +138,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
138138
bool hasVInstructionsF16() const { return HasStdExtV && hasStdExtZfh(); }
139139
bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); }
140140
bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); }
141-
// D and Zfh imply F.
142-
bool hasVInstructionsAnyF() const { return HasStdExtV && hasStdExtF(); }
141+
// F16 and F64 both require F32.
142+
bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
143143
unsigned getMaxInterleaveFactor() const {
144144
return hasVInstructions() ? MaxInterleaveFactor : 1;
145145
}

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