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[X86][FastISel] Handle CRC32 intrinsics
Some applications make heavy use of the crc32 operation (e.g., as part of a hash function), so having a FastISel path avoids fallbacks to SelectionDAG and improves compile times, in our case by ~1.5%. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D148023
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‎llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3030,6 +3030,58 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
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updateValueMap(II, ResultReg);
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return true;
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}
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case Intrinsic::x86_sse42_crc32_32_8:
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case Intrinsic::x86_sse42_crc32_32_16:
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case Intrinsic::x86_sse42_crc32_32_32:
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case Intrinsic::x86_sse42_crc32_64_64: {
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if (!Subtarget->hasCRC32())
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return false;
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Type *RetTy = II->getCalledFunction()->getReturnType();
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MVT VT;
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if (!isTypeLegal(RetTy, VT))
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return false;
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unsigned Opc;
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const TargetRegisterClass *RC = nullptr;
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switch (II->getIntrinsicID()) {
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default:
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llvm_unreachable("Unexpected intrinsic.");
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case Intrinsic::x86_sse42_crc32_32_8:
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Opc = X86::CRC32r32r8;
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RC = &X86::GR32RegClass;
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break;
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case Intrinsic::x86_sse42_crc32_32_16:
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Opc = X86::CRC32r32r16;
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RC = &X86::GR32RegClass;
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break;
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case Intrinsic::x86_sse42_crc32_32_32:
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Opc = X86::CRC32r32r32;
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RC = &X86::GR32RegClass;
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break;
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case Intrinsic::x86_sse42_crc32_64_64:
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Opc = X86::CRC32r64r64;
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RC = &X86::GR64RegClass;
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break;
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}
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const Value *LHS = II->getArgOperand(0);
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const Value *RHS = II->getArgOperand(1);
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Register LHSReg = getRegForValue(LHS);
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Register RHSReg = getRegForValue(RHS);
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if (!LHSReg || !RHSReg)
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return false;
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Register ResultReg = fastEmitInst_rr(Opc, RC, LHSReg, RHSReg);
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if (!ResultReg)
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return false;
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updateValueMap(II, ResultReg);
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return true;
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}
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}
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}
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‎llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no-generate-body-for-unused-prefixes
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; i686 uses -fast-isel-abort=1 only as argument lowering is not supported, so check that FastISel didn't miss the call.
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; RUN: llc < %s -fast-isel -pass-remarks-missed=sdagisel -mtriple=i686-unknown-unknown -mattr=+crc32 2>&1 >/dev/null | FileCheck %s -check-prefix=STDERR-X86 -allow-empty
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=i686-unknown-unknown -mattr=-sse4.2,+crc32 | FileCheck %s -check-prefix=X86
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=i686-unknown-unknown -mattr=+crc32 | FileCheck %s -check-prefix=X86
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; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-unknown-unknown -mattr=-sse4.2,+crc32 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-unknown-unknown -mattr=+crc32 | FileCheck %s -check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c
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; STDERR-X86-NOT: FastISel missed call: %res = call i32 @llvm.x86.sse42.crc32
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; Note: %a1 is i32 as FastISel can't handle i8/i16 arguments.
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define i32 @test_mm_crc32_u8(i32 %a0, i32 %a1) nounwind {
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; X86-LABEL: test_mm_crc32_u8:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: crc32b %cl, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm_crc32_u8:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: crc32b %sil, %eax
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; X64-NEXT: retq
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%trunc = trunc i32 %a1 to i8
28+
%res = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a0, i8 %trunc)
29+
ret i32 %res
30+
}
31+
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind readnone
32+
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; Note: %a1 is i32 as FastISel can't handle i8/i16 arguments.
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define i32 @test_mm_crc32_u16(i32 %a0, i32 %a1) nounwind {
35+
; X86-LABEL: test_mm_crc32_u16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: crc32w %cx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm_crc32_u16:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: crc32w %si, %eax
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; X64-NEXT: retq
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%trunc = trunc i32 %a1 to i16
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%res = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a0, i16 %trunc)
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ret i32 %res
50+
}
51+
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind readnone
52+
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define i32 @test_mm_crc32_u32(i32 %a0, i32 %a1) nounwind {
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; X86-LABEL: test_mm_crc32_u32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: crc32l {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm_crc32_u32:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: crc32l %esi, %eax
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; X64-NEXT: retq
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%res = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a0, i32 %a1)
66+
ret i32 %res
67+
}
68+
declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind readnone

‎llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,18 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=-sse4.2,+crc32 | FileCheck %s
3-
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+crc32 | FileCheck %s
2+
; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-unknown-unknown -mattr=-sse4.2,+crc32 | FileCheck %s
3+
; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-unknown-unknown -mattr=+crc32 | FileCheck %s
44

55
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c
66

7-
define i64 @test_mm_crc64_u8(i64 %a0, i8 %a1) nounwind{
7+
; Note: %a1 is i32 as FastISel can't handle i8/i16 arguments.
8+
define i64 @test_mm_crc64_u8(i64 %a0, i32 %a1) nounwind{
89
; CHECK-LABEL: test_mm_crc64_u8:
910
; CHECK: # %bb.0:
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; CHECK-NEXT: crc32b %sil, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
13-
%res = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a0, i8 %a1)
14+
%trunc = trunc i32 %a1 to i8
15+
%res = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a0, i8 %trunc)
1416
ret i64 %res
1517
}
1618
declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind readnone

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