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AMDGPU: Cleanup MIR test
Remove registers section and compact block/register numbers
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‎llvm/test/CodeGen/AMDGPU/spill-before-exec.mir

Lines changed: 50 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -11,103 +11,76 @@ tracksRegLiveness: true
1111
machineFunctionInfo:
1212
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
1313
stackPtrOffsetReg: $sgpr32
14-
registers:
15-
- { id: 0, class: sreg_64 }
16-
- { id: 1100, class: sgpr_128 }
17-
- { id: 1101, class: sgpr_128 }
18-
- { id: 1102, class: sgpr_128 }
19-
- { id: 1103, class: sgpr_128 }
20-
- { id: 1104, class: sgpr_128 }
21-
- { id: 1105, class: sgpr_128 }
22-
- { id: 1106, class: sgpr_128 }
23-
- { id: 1107, class: sgpr_128 }
24-
- { id: 1108, class: sgpr_128 }
25-
- { id: 1109, class: sgpr_128 }
26-
- { id: 1110, class: sgpr_128 }
27-
- { id: 1111, class: sgpr_128 }
28-
- { id: 1112, class: sgpr_128 }
29-
- { id: 1113, class: sgpr_128 }
30-
- { id: 1114, class: sgpr_128 }
31-
- { id: 1115, class: sgpr_128 }
32-
- { id: 1116, class: sgpr_128 }
33-
- { id: 1117, class: sgpr_128 }
34-
- { id: 1118, class: sgpr_128 }
35-
- { id: 1119, class: sgpr_128 }
36-
- { id: 1120, class: sgpr_128 }
37-
- { id: 1121, class: sgpr_128 }
38-
- { id: 1122, class: sgpr_128 }
39-
- { id: 1123, class: sgpr_128 }
40-
- { id: 1124, class: sgpr_128 }
41-
- { id: 1125, class: sgpr_128 }
4214
body: |
4315
bb.0:
44-
successors: %bb.1
4516
liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr100_sgpr101, $sgpr102_sgpr103
17+
4618
%0:sreg_64 = COPY $sgpr102_sgpr103
47-
%1100 = COPY $sgpr100_sgpr101_sgpr102_sgpr103
48-
%1101 = COPY %1100
49-
%1102 = COPY %1100
50-
%1103 = COPY %1100
51-
%1104 = COPY %1100
52-
%1105 = COPY %1100
53-
%1106 = COPY %1100
54-
%1107 = COPY %1100
55-
%1108 = COPY %1100
56-
%1109 = COPY %1100
57-
%1110 = COPY %1100
58-
%1111 = COPY %1100
59-
%1112 = COPY %1100
60-
%1113 = COPY %1100
61-
%1114 = COPY %1100
62-
%1115 = COPY %1100
63-
%1116 = COPY %1100
64-
%1117 = COPY %1100
65-
%1118 = COPY %1100
66-
%1119 = COPY %1100
67-
%1120 = COPY %1100
68-
%1121 = COPY %1100
69-
%1122 = COPY %1100
70-
%1123 = COPY %1100
71-
%1124 = COPY %1100
72-
%1125 = COPY %1100
19+
%1:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103
20+
%2:sgpr_128 = COPY %1
21+
%3:sgpr_128 = COPY %1
22+
%4:sgpr_128 = COPY %1
23+
%5:sgpr_128 = COPY %1
24+
%6:sgpr_128 = COPY %1
25+
%7:sgpr_128 = COPY %1
26+
%8:sgpr_128 = COPY %1
27+
%9:sgpr_128 = COPY %1
28+
%10:sgpr_128 = COPY %1
29+
%11:sgpr_128 = COPY %1
30+
%12:sgpr_128 = COPY %1
31+
%13:sgpr_128 = COPY %1
32+
%14:sgpr_128 = COPY %1
33+
%15:sgpr_128 = COPY %1
34+
%16:sgpr_128 = COPY %1
35+
%17:sgpr_128 = COPY %1
36+
%18:sgpr_128 = COPY %1
37+
%19:sgpr_128 = COPY %1
38+
%20:sgpr_128 = COPY %1
39+
%21:sgpr_128 = COPY %1
40+
%22:sgpr_128 = COPY %1
41+
%23:sgpr_128 = COPY %1
42+
%24:sgpr_128 = COPY %1
43+
%25:sgpr_128 = COPY %1
44+
%26:sgpr_128 = COPY %1
7345
S_BRANCH %bb.1
7446
7547
bb.1:
7648
liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr102_sgpr103
77-
%0 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec
49+
50+
%0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec
7851
$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
79-
SI_MASK_BRANCH %bb.100, implicit $exec
52+
SI_MASK_BRANCH %bb.3, implicit $exec
8053
S_BRANCH %bb.2
8154
8255
bb.2:
8356
liveins: $sgpr98_sgpr99, $sgpr102_sgpr103
57+
8458
%0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr98_sgpr99, implicit-def $exec, implicit-def $scc, implicit $exec
8559
$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
86-
SI_MASK_BRANCH %bb.100, implicit $exec
87-
S_BRANCH %bb.200
60+
SI_MASK_BRANCH %bb.3, implicit $exec
61+
S_BRANCH %bb.4
8862
89-
bb.100:
63+
bb.3:
9064
liveins: $sgpr102_sgpr103
65+
9166
%0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr102_sgpr103, implicit-def $exec, implicit-def $scc, implicit $exec
9267
$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
93-
S_BRANCH %bb.200
94-
95-
bb.200:
96-
S_CMP_EQ_U64 %1100.sub0_sub1, %1101.sub2_sub3, implicit-def $scc
97-
S_CMP_EQ_U64 %1102.sub0_sub1, %1103.sub2_sub3, implicit-def $scc
98-
S_CMP_EQ_U64 %1104.sub0_sub1, %1105.sub2_sub3, implicit-def $scc
99-
S_CMP_EQ_U64 %1106.sub0_sub1, %1107.sub2_sub3, implicit-def $scc
100-
S_CMP_EQ_U64 %1108.sub0_sub1, %1109.sub2_sub3, implicit-def $scc
101-
S_CMP_EQ_U64 %1110.sub0_sub1, %1111.sub2_sub3, implicit-def $scc
102-
S_CMP_EQ_U64 %1112.sub0_sub1, %1113.sub2_sub3, implicit-def $scc
103-
S_CMP_EQ_U64 %1114.sub0_sub1, %1115.sub2_sub3, implicit-def $scc
104-
S_CMP_EQ_U64 %1116.sub0_sub1, %1117.sub2_sub3, implicit-def $scc
105-
S_CMP_EQ_U64 %1118.sub0_sub1, %1119.sub2_sub3, implicit-def $scc
106-
S_CMP_EQ_U64 %1120.sub0_sub1, %1121.sub2_sub3, implicit-def $scc
107-
S_CMP_EQ_U64 %1122.sub0_sub1, %1123.sub2_sub3, implicit-def $scc
108-
S_CMP_EQ_U64 %1124.sub0_sub1, %1125.sub2_sub3, implicit-def $scc
68+
S_BRANCH %bb.4
10969
70+
bb.4:
71+
S_CMP_EQ_U64 %1.sub0_sub1, %2.sub2_sub3, implicit-def $scc
72+
S_CMP_EQ_U64 %3.sub0_sub1, %4.sub2_sub3, implicit-def $scc
73+
S_CMP_EQ_U64 %5.sub0_sub1, %6.sub2_sub3, implicit-def $scc
74+
S_CMP_EQ_U64 %7.sub0_sub1, %8.sub2_sub3, implicit-def $scc
75+
S_CMP_EQ_U64 %9.sub0_sub1, %10.sub2_sub3, implicit-def $scc
76+
S_CMP_EQ_U64 %11.sub0_sub1, %12.sub2_sub3, implicit-def $scc
77+
S_CMP_EQ_U64 %13.sub0_sub1, %14.sub2_sub3, implicit-def $scc
78+
S_CMP_EQ_U64 %15.sub0_sub1, %16.sub2_sub3, implicit-def $scc
79+
S_CMP_EQ_U64 %17.sub0_sub1, %18.sub2_sub3, implicit-def $scc
80+
S_CMP_EQ_U64 %19.sub0_sub1, %20.sub2_sub3, implicit-def $scc
81+
S_CMP_EQ_U64 %21.sub0_sub1, %22.sub2_sub3, implicit-def $scc
82+
S_CMP_EQ_U64 %23.sub0_sub1, %24.sub2_sub3, implicit-def $scc
83+
S_CMP_EQ_U64 %25.sub0_sub1, %26.sub2_sub3, implicit-def $scc
11084
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
11185
S_SETPC_B64_return undef $sgpr30_sgpr31, implicit %0, implicit $vgpr0
112-
11386
...

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