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[RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (llvm#115402)
We don't add a custom node for REMW as we can detect it with (srem (sexti32), (sexti32)).
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6 files changed

+132
-182
lines changed

6 files changed

+132
-182
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -456,11 +456,17 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
456456
}
457457

458458
if (ST.hasStdExtM()) {
459-
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
460-
.legalFor({s32, sXLen})
459+
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM})
460+
.legalFor({sXLen})
461+
.customFor({s32})
461462
.libcallFor({sDoubleXLen})
462463
.clampScalar(0, s32, sDoubleXLen)
463464
.widenScalarToNextPow2(0);
465+
getActionDefinitionsBuilder(G_SREM)
466+
.legalFor({sXLen})
467+
.libcallFor({sDoubleXLen})
468+
.clampScalar(0, sXLen, sDoubleXLen)
469+
.widenScalarToNextPow2(0);
464470
} else {
465471
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
466472
.libcallFor({sXLen, sDoubleXLen})
@@ -1165,6 +1171,12 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
11651171
switch (Opcode) {
11661172
default:
11671173
llvm_unreachable("Unexpected opcode");
1174+
case TargetOpcode::G_SDIV:
1175+
return RISCV::G_DIVW;
1176+
case TargetOpcode::G_UDIV:
1177+
return RISCV::G_DIVUW;
1178+
case TargetOpcode::G_UREM:
1179+
return RISCV::G_REMUW;
11681180
case TargetOpcode::G_ROTL:
11691181
return RISCV::G_ROLW;
11701182
case TargetOpcode::G_ROTR:
@@ -1216,6 +1228,9 @@ bool RISCVLegalizerInfo::legalizeCustom(
12161228
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
12171229
LegalizerHelper::Legalized;
12181230
}
1231+
case TargetOpcode::G_SDIV:
1232+
case TargetOpcode::G_UDIV:
1233+
case TargetOpcode::G_UREM:
12191234
case TargetOpcode::G_ROTL:
12201235
case TargetOpcode::G_ROTR: {
12211236
Helper.Observer.changingInstr(MI);

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -246,13 +246,6 @@ let Predicates = [HasStdExtZmmul, IsRV64] in {
246246
def : PatGprGpr<mul, MULW, i32, i32>;
247247
}
248248

249-
let Predicates = [HasStdExtM, IsRV64] in {
250-
def : PatGprGpr<sdiv, DIVW, i32, i32>;
251-
def : PatGprGpr<udiv, DIVUW, i32, i32>;
252-
def : PatGprGpr<srem, REMW, i32, i32>;
253-
def : PatGprGpr<urem, REMUW, i32, i32>;
254-
}
255-
256249
//===----------------------------------------------------------------------===//
257250
// Zb* RV64 i32 patterns not used by SelectionDAG.
258251
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrGISel.td

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,30 @@ class RISCVGenericInstruction : GenericInstruction {
1717
let Namespace = "RISCV";
1818
}
1919

20+
// Pseudo equivalent to a RISCVISD::DIVW.
21+
def G_DIVW : RISCVGenericInstruction {
22+
let OutOperandList = (outs type0:$dst);
23+
let InOperandList = (ins type0:$src1, type0:$src2);
24+
let hasSideEffects = false;
25+
}
26+
def : GINodeEquiv<G_DIVW, riscv_divw>;
27+
28+
// Pseudo equivalent to a RISCVISD::DIVUW.
29+
def G_DIVUW : RISCVGenericInstruction {
30+
let OutOperandList = (outs type0:$dst);
31+
let InOperandList = (ins type0:$src1, type0:$src2);
32+
let hasSideEffects = false;
33+
}
34+
def : GINodeEquiv<G_DIVUW, riscv_divuw>;
35+
36+
// Pseudo equivalent to a RISCVISD::REMUW.
37+
def G_REMUW : RISCVGenericInstruction {
38+
let OutOperandList = (outs type0:$dst);
39+
let InOperandList = (ins type0:$src1, type0:$src2);
40+
let hasSideEffects = false;
41+
}
42+
def : GINodeEquiv<G_REMUW, riscv_remuw>;
43+
2044
// Pseudo equivalent to a RISCVISD::RORW.
2145
def G_RORW : RISCVGenericInstruction {
2246
let OutOperandList = (outs type0:$dst);

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

Lines changed: 9 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -47,39 +47,9 @@ body: |
4747
; RV64I-NEXT: $x10 = COPY [[DIVW]]
4848
; RV64I-NEXT: PseudoRET implicit $x10
4949
%0:gprb(s64) = COPY $x10
50-
%1:gprb(s32) = G_TRUNC %0(s64)
51-
%2:gprb(s64) = COPY $x11
52-
%3:gprb(s32) = G_TRUNC %2(s64)
53-
%4:gprb(s32) = G_SDIV %1, %3
54-
%5:gprb(s64) = G_ANYEXT %4(s32)
55-
$x10 = COPY %5(s64)
56-
PseudoRET implicit $x10
57-
58-
...
59-
---
60-
name: srem_i32
61-
legalized: true
62-
regBankSelected: true
63-
tracksRegLiveness: true
64-
body: |
65-
bb.0.entry:
66-
liveins: $x10, $x11
67-
68-
; RV64I-LABEL: name: srem_i32
69-
; RV64I: liveins: $x10, $x11
70-
; RV64I-NEXT: {{ $}}
71-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
72-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
73-
; RV64I-NEXT: [[REMW:%[0-9]+]]:gpr = REMW [[COPY]], [[COPY1]]
74-
; RV64I-NEXT: $x10 = COPY [[REMW]]
75-
; RV64I-NEXT: PseudoRET implicit $x10
76-
%0:gprb(s64) = COPY $x10
77-
%1:gprb(s32) = G_TRUNC %0(s64)
78-
%2:gprb(s64) = COPY $x11
79-
%3:gprb(s32) = G_TRUNC %2(s64)
80-
%4:gprb(s32) = G_SREM %1, %3
81-
%5:gprb(s64) = G_ANYEXT %4(s32)
82-
$x10 = COPY %5(s64)
50+
%1:gprb(s64) = COPY $x11
51+
%2:gprb(s64) = G_DIVW %0, %1
52+
$x10 = COPY %2(s64)
8353
PseudoRET implicit $x10
8454
8555
...
@@ -101,12 +71,9 @@ body: |
10171
; RV64I-NEXT: $x10 = COPY [[DIVUW]]
10272
; RV64I-NEXT: PseudoRET implicit $x10
10373
%0:gprb(s64) = COPY $x10
104-
%1:gprb(s32) = G_TRUNC %0(s64)
105-
%2:gprb(s64) = COPY $x11
106-
%3:gprb(s32) = G_TRUNC %2(s64)
107-
%4:gprb(s32) = G_UDIV %1, %3
108-
%5:gprb(s64) = G_ANYEXT %4(s32)
109-
$x10 = COPY %5(s64)
74+
%1:gprb(s64) = COPY $x11
75+
%2:gprb(s64) = G_DIVUW %0, %1
76+
$x10 = COPY %2(s64)
11077
PseudoRET implicit $x10
11178
11279
...
@@ -128,12 +95,9 @@ body: |
12895
; RV64I-NEXT: $x10 = COPY [[REMUW]]
12996
; RV64I-NEXT: PseudoRET implicit $x10
13097
%0:gprb(s64) = COPY $x10
131-
%1:gprb(s32) = G_TRUNC %0(s64)
132-
%2:gprb(s64) = COPY $x11
133-
%3:gprb(s32) = G_TRUNC %2(s64)
134-
%4:gprb(s32) = G_UREM %1, %3
135-
%5:gprb(s64) = G_ANYEXT %4(s32)
136-
$x10 = COPY %5(s64)
98+
%1:gprb(s64) = COPY $x11
99+
%2:gprb(s64) = G_REMUW %0, %1
100+
$x10 = COPY %2(s64)
137101
PseudoRET implicit $x10
138102
139103
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir

Lines changed: 40 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -27,16 +27,13 @@ body: |
2727
; CHECK-M-LABEL: name: sdiv_i8
2828
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
2929
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
30-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
31-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
32-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
33-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
34-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
35-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]](s32)
36-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
37-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
38-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
39-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
30+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
31+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
32+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
33+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64)
34+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
35+
; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]]
36+
; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64)
4037
; CHECK-M-NEXT: PseudoRET implicit $x10
4138
%0:_(s64) = COPY $x10
4239
%1:_(s64) = COPY $x11
@@ -72,16 +69,13 @@ body: |
7269
; CHECK-M-LABEL: name: sdiv_i15
7370
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
7471
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
75-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
76-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
77-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
78-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
79-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
80-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]](s32)
81-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
82-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
83-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
84-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
72+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
73+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
74+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
75+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64)
76+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
77+
; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]]
78+
; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64)
8579
; CHECK-M-NEXT: PseudoRET implicit $x10
8680
%0:_(s64) = COPY $x10
8781
%1:_(s64) = COPY $x11
@@ -117,16 +111,13 @@ body: |
117111
; CHECK-M-LABEL: name: sdiv_i16
118112
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
119113
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
120-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
121-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
122-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
123-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
124-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
125-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]](s32)
126-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
127-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
128-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
129-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
114+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
115+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
116+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
117+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64)
118+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64)
119+
; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]]
120+
; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64)
130121
; CHECK-M-NEXT: PseudoRET implicit $x10
131122
%0:_(s64) = COPY $x10
132123
%1:_(s64) = COPY $x11
@@ -159,11 +150,8 @@ body: |
159150
; CHECK-M-LABEL: name: sdiv_i32
160151
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
161152
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
162-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
163-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
164-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
165-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
166-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
153+
; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[COPY]], [[COPY1]]
154+
; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64)
167155
; CHECK-M-NEXT: PseudoRET implicit $x10
168156
%0:_(s64) = COPY $x10
169157
%1:_(s64) = COPY $x11
@@ -343,14 +331,11 @@ body: |
343331
; CHECK-M-LABEL: name: udiv_i8
344332
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
345333
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
346-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
347-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
348-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
349-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
350-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
351-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
352-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
353-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
334+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
335+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
336+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
337+
; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]]
338+
; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64)
354339
; CHECK-M-NEXT: PseudoRET implicit $x10
355340
%0:_(s64) = COPY $x10
356341
%1:_(s64) = COPY $x11
@@ -384,14 +369,11 @@ body: |
384369
; CHECK-M-LABEL: name: udiv_i15
385370
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
386371
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
387-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
388-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
389-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
390-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
391-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
392-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
393-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
394-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
372+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
373+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
374+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
375+
; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]]
376+
; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64)
395377
; CHECK-M-NEXT: PseudoRET implicit $x10
396378
%0:_(s64) = COPY $x10
397379
%1:_(s64) = COPY $x11
@@ -425,14 +407,11 @@ body: |
425407
; CHECK-M-LABEL: name: udiv_i16
426408
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
427409
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
428-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
429-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
430-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
431-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
432-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
433-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
434-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
435-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
410+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
411+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
412+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
413+
; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]]
414+
; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64)
436415
; CHECK-M-NEXT: PseudoRET implicit $x10
437416
%0:_(s64) = COPY $x10
438417
%1:_(s64) = COPY $x11
@@ -466,11 +445,8 @@ body: |
466445
; CHECK-M-LABEL: name: udiv_i32
467446
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
468447
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
469-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
470-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
471-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[TRUNC]], [[TRUNC1]]
472-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
473-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
448+
; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[COPY]], [[COPY1]]
449+
; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64)
474450
; CHECK-M-NEXT: PseudoRET implicit $x10
475451
%0:_(s64) = COPY $x10
476452
%1:_(s64) = COPY $x11

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