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[AMDGPU] Remove scratch rsrc from spill pseudos
Differential Revision: https://reviews.llvm.org/D91110
1 parent fa9f413 commit 5ab1702

30 files changed

+757
-252
lines changed

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -375,6 +375,18 @@ void SIFrameLowering::emitEntryFunctionFlatScratchInit(
375375
.addImm(8);
376376
}
377377

378+
// Note SGPRSpill stack IDs should only be used for SGPR spilling to VGPRs, not
379+
// memory. They should have been removed by now.
380+
static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
381+
for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
382+
I != E; ++I) {
383+
if (!MFI.isDeadObjectIndex(I))
384+
return false;
385+
}
386+
387+
return true;
388+
}
389+
378390
// Shift down registers reserved for the scratch RSRC.
379391
Register SIFrameLowering::getEntryFunctionReservedScratchRsrcReg(
380392
MachineFunction &MF) const {
@@ -389,7 +401,8 @@ Register SIFrameLowering::getEntryFunctionReservedScratchRsrcReg(
389401

390402
Register ScratchRsrcReg = MFI->getScratchRSrcReg();
391403

392-
if (!ScratchRsrcReg || !MRI.isPhysRegUsed(ScratchRsrcReg))
404+
if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&
405+
allStackObjectsAreDead(MF.getFrameInfo())))
393406
return Register();
394407

395408
if (ST.hasSGPRInitBug() ||
@@ -1131,18 +1144,6 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
11311144
}
11321145
}
11331146

1134-
// Note SGPRSpill stack IDs should only be used for SGPR spilling to VGPRs, not
1135-
// memory. They should have been removed by now.
1136-
static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
1137-
for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
1138-
I != E; ++I) {
1139-
if (!MFI.isDeadObjectIndex(I))
1140-
return false;
1141-
}
1142-
1143-
return true;
1144-
}
1145-
11461147
#ifndef NDEBUG
11471148
static bool allSGPRSpillsAreDead(const MachineFunction &MF) {
11481149
const MachineFrameInfo &MFI = MF.getFrameInfo();

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1379,18 +1379,12 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
13791379
MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
13801380
}
13811381

1382-
Register ScratchRSrc =
1383-
ST.enableFlatScratch() ? AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3 // Dummy
1384-
: MFI->getScratchRSrcReg();
13851382
BuildMI(MBB, MI, DL, OpDesc)
13861383
.addReg(SrcReg, getKillRegState(isKill)) // data
13871384
.addFrameIndex(FrameIndex) // addr
13881385
.addMemOperand(MMO)
1389-
.addReg(ScratchRSrc, RegState::Implicit)
13901386
.addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1391-
// Add the scratch resource registers as implicit uses because we may end up
1392-
// needing them, and need to ensure that the reserved registers are
1393-
// correctly handled.
1387+
13941388
if (RI.spillSGPRToVGPR())
13951389
FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
13961390
return;
@@ -1400,13 +1394,9 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
14001394
: getVGPRSpillSaveOpcode(SpillSize);
14011395
MFI->setHasSpilledVGPRs();
14021396

1403-
Register ScratchRSrc =
1404-
ST.enableFlatScratch() ? AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3 // Dummy
1405-
: MFI->getScratchRSrcReg();
14061397
BuildMI(MBB, MI, DL, get(Opcode))
14071398
.addReg(SrcReg, getKillRegState(isKill)) // data
14081399
.addFrameIndex(FrameIndex) // addr
1409-
.addReg(ScratchRSrc) // scratch_rsrc
14101400
.addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
14111401
.addImm(0) // offset
14121402
.addMemOperand(MMO);
@@ -1519,27 +1509,20 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
15191509
MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
15201510
}
15211511

1522-
Register ScratchRSrc =
1523-
ST.enableFlatScratch() ? AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3 // Dummy
1524-
: MFI->getScratchRSrcReg();
15251512
if (RI.spillSGPRToVGPR())
15261513
FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
15271514
BuildMI(MBB, MI, DL, OpDesc, DestReg)
15281515
.addFrameIndex(FrameIndex) // addr
15291516
.addMemOperand(MMO)
1530-
.addReg(ScratchRSrc, RegState::Implicit)
15311517
.addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1518+
15321519
return;
15331520
}
15341521

15351522
unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
15361523
: getVGPRSpillRestoreOpcode(SpillSize);
1537-
Register ScratchRSrc =
1538-
ST.enableFlatScratch() ? AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3 // Dummy
1539-
: MFI->getScratchRSrcReg();
15401524
BuildMI(MBB, MI, DL, get(Opcode), DestReg)
15411525
.addFrameIndex(FrameIndex) // vaddr
1542-
.addReg(ScratchRSrc) // scratch_rsrc
15431526
.addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
15441527
.addImm(0) // offset
15451528
.addMemOperand(MMO);

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -644,7 +644,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class, bit UsesTmp = 0> {
644644
SchedRW = [WriteVMEM] in {
645645
def _SAVE : VPseudoInstSI <
646646
(outs),
647-
(ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$srsrc,
647+
(ins vgpr_class:$vdata, i32imm:$vaddr,
648648
SReg_32:$soffset, i32imm:$offset)> {
649649
let mayStore = 1;
650650
let mayLoad = 0;
@@ -656,8 +656,8 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class, bit UsesTmp = 0> {
656656

657657
def _RESTORE : VPseudoInstSI <
658658
(outs vgpr_class:$vdata),
659-
(ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
660-
i32imm:$offset)> {
659+
(ins i32imm:$vaddr,
660+
SReg_32:$soffset, i32imm:$offset)> {
661661
let mayStore = 0;
662662
let mayLoad = 1;
663663

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -748,7 +748,6 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI,
748748
int Index,
749749
Register ValueReg,
750750
bool IsKill,
751-
MCRegister ScratchRsrcReg,
752751
MCRegister ScratchOffsetReg,
753752
int64_t InstOffset,
754753
MachineMemOperand *MMO,
@@ -888,7 +887,7 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI,
888887
.addReg(SubReg,
889888
getDefRegState(!IsStore) | getKillRegState(IsKill));
890889
if (!IsFlat)
891-
MIB.addReg(ScratchRsrcReg);
890+
MIB.addReg(FuncInfo->getScratchRSrcReg());
892891

893892
if (SOffset == AMDGPU::NoRegister) {
894893
if (!IsFlat)
@@ -1009,14 +1008,14 @@ void SIRegisterInfo::buildSGPRSpillLoadStore(MachineBasicBlock::iterator MI,
10091008
buildSpillLoadStore(MI, Opc,
10101009
Index,
10111010
VGPR, false,
1012-
MFI->getScratchRSrcReg(), FrameReg,
1011+
FrameReg,
10131012
Offset * EltSize, MMO,
10141013
RS);
10151014
} else {
10161015
unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
10171016
: AMDGPU::BUFFER_STORE_DWORD_OFFSET;
10181017
buildSpillLoadStore(MI, Opc, Index, VGPR,
1019-
IsKill, MFI->getScratchRSrcReg(), FrameReg,
1018+
IsKill, FrameReg,
10201019
Offset * EltSize, MMO, RS);
10211020
// This only ever adds one VGPR spill
10221021
MFI->addToSpilledVGPRs(1);
@@ -1354,7 +1353,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
13541353
buildSpillLoadStore(MI, Opc,
13551354
Index,
13561355
VData->getReg(), VData->isKill(),
1357-
TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
13581356
FrameReg,
13591357
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
13601358
*MI->memoperands_begin(),
@@ -1390,7 +1388,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
13901388
buildSpillLoadStore(MI, Opc,
13911389
Index,
13921390
VData->getReg(), VData->isKill(),
1393-
TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
13941391
FrameReg,
13951392
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
13961393
*MI->memoperands_begin(),

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,6 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
334334
int Index,
335335
Register ValueReg,
336336
bool ValueIsKill,
337-
MCRegister ScratchRsrcReg,
338337
MCRegister ScratchOffsetReg,
339338
int64_t InstrOffset,
340339
MachineMemOperand *MMO,

‎llvm/test/CodeGen/AMDGPU/addrspacecast.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -342,7 +342,7 @@ end:
342342
; HSA-LABEL: {{^}}store_flat_scratch:
343343
; CI-DAG: s_mov_b32 flat_scratch_lo, s9
344344
; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11
345-
; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
345+
; CI-DAG: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
346346

347347
; GFX9: s_add_u32 flat_scratch_lo, s6, s9
348348
; GFX9: s_addc_u32 flat_scratch_hi, s7, 0

‎llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@ body: |
4646
; CHECK: liveins: $vgpr0
4747
; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
4848
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
49-
; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
49+
; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
5050
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
51-
; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
51+
; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
5252
; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $sgpr4_sgpr5, implicit $exec
5353
; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed renamable $vcc
5454
%0:vgpr_32 = COPY $vgpr0

‎llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,10 @@ body: |
1313
; GCN: bb.0:
1414
; GCN: successors: %bb.1(0x80000000)
1515
; GCN: liveins: $vgpr0_vgpr1
16-
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
16+
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
1717
; GCN: bb.1:
1818
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
19-
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
19+
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
2020
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
2121
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec
2222
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
@@ -48,14 +48,14 @@ body: |
4848
; GCN: bb.0:
4949
; GCN: successors: %bb.1(0x80000000)
5050
; GCN: liveins: $vgpr0_vgpr1
51-
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
51+
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
5252
; GCN: bb.1:
5353
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
54-
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
54+
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
5555
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
5656
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
5757
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
58-
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
58+
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
5959
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
6060
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
6161
; GCN: bb.2:
@@ -90,12 +90,12 @@ body: |
9090
; GCN: bb.0:
9191
; GCN: successors: %bb.1(0x80000000)
9292
; GCN: liveins: $vgpr0_vgpr1
93-
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
93+
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
9494
; GCN: bb.1:
9595
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
96-
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
96+
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
9797
; GCN: renamable $vgpr2 = V_ADD_U32_e32 1, undef $vgpr0, implicit $exec
98-
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
98+
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
9999
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
100100
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
101101
; GCN: bb.2:
@@ -126,13 +126,13 @@ body: |
126126
; GCN: bb.0:
127127
; GCN: successors: %bb.1(0x80000000)
128128
; GCN: liveins: $vgpr0_vgpr1
129-
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
129+
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
130130
; GCN: bb.1:
131131
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
132-
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
132+
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
133133
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, undef renamable $vgpr0, 0, 0, 0, 0, implicit $exec
134134
; GCN: renamable $vgpr0 = V_ADD_U32_e64 1, 1, 0, implicit $exec
135-
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
135+
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.1, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
136136
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
137137
; GCN: bb.2:
138138
; GCN: S_ENDPGM 0
@@ -162,10 +162,10 @@ body: |
162162
; GCN: bb.0:
163163
; GCN: successors: %bb.1(0x80000000)
164164
; GCN: liveins: $vgpr0_vgpr1
165-
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
165+
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
166166
; GCN: bb.1:
167167
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
168-
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
168+
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
169169
; GCN: undef renamable $vgpr3 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit-def dead $vgpr2_vgpr3
170170
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, undef renamable $vgpr1, 0, 0, 0, 0, implicit $exec
171171
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec

‎llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,4 +46,4 @@ body: |
4646
liveins: $sgpr4, $sgpr5, $sgpr9, $sgpr22, $vgpr0, $sgpr6_sgpr7
4747
4848
renamable $vgpr2 = IMPLICIT_DEF
49-
SI_SPILL_V32_SAVE killed $vgpr2, %stack.0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
49+
SI_SPILL_V32_SAVE killed $vgpr2, %stack.0, $sgpr32, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)

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