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[VE] Change to promote i32 AND/OR/XOR operations
VE has only 64 bits AND/OR/XOR instructions. We pretended that VE has 32 bits instructions also, but doing it increase the number of generated instructions. Therefore, we decide to promote 32 bits operations and use only 64 bits instructions in back end. We also avoid pretending that VE has 32 bits LEA instruction. Update regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85726
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10 files changed

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‎llvm/lib/Target/VE/VEISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -696,6 +696,12 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
696696
setOperationAction(ISD::CTLZ, IntVT, Act);
697697
setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
698698
setOperationAction(ISD::CTPOP, IntVT, Act);
699+
700+
// VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
701+
// Use isel patterns for i64, promote for i32.
702+
setOperationAction(ISD::AND, IntVT, Act);
703+
setOperationAction(ISD::OR, IntVT, Act);
704+
setOperationAction(ISD::XOR, IntVT, Act);
699705
}
700706
/// } Int Ops
701707

‎llvm/lib/Target/VE/VEInstrInfo.td

Lines changed: 23 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -917,16 +917,11 @@ let cx = 0, DecoderMethod = "DecodeLoadI64" in
917917
defm LEA : RMm<"lea", 0x06, I64>;
918918
let cx = 1, DecoderMethod = "DecodeLoadI64" in
919919
defm LEASL : RMm<"lea.sl", 0x06, I64>;
920-
let cx = 0, DecoderMethod = "DecodeLoadI32", isCodeGenOnly = 1 in
921-
defm LEA32 : RMm<"lea", 0x06, I32>;
922920

923921
def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
924922
def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
925923
def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
926924
def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;
927-
def : Pat<(add I32:$base, simm32:$disp),
928-
(LEA32rii (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $base, sub_i32), 0,
929-
(LO32 $disp))>;
930925

931926
def lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp),
932927
[(add (add node:$base, node:$idx), node:$disp),
@@ -1181,15 +1176,12 @@ let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
11811176

11821177
// Section 8.5.1 - AND (AND)
11831178
defm AND : RRm<"and", 0x44, I64, i64, and>;
1184-
let isCodeGenOnly = 1 in defm AND32 : RRm<"and", 0x44, I32, i32, and>;
11851179

11861180
// Section 8.5.2 - OR (OR)
11871181
defm OR : RRm<"or", 0x45, I64, i64, or>;
1188-
let isCodeGenOnly = 1 in defm OR32 : RRm<"or", 0x45, I32, i32, or>;
11891182

11901183
// Section 8.5.3 - XOR (Exclusive OR)
11911184
defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
1192-
let isCodeGenOnly = 1 in defm XOR32 : RRm<"xor", 0x46, I32, i32, xor>;
11931185

11941186
// Section 8.5.4 - EQV (Equivalence)
11951187
defm EQV : RRm<"eqv", 0x47, I64, i64>;
@@ -1495,10 +1487,11 @@ defm SHMB : SHMm<"shm.b", 0x31, I64>;
14951487
//===----------------------------------------------------------------------===//
14961488

14971489
// Small immediates.
1498-
def : Pat<(i32 simm7:$val), (OR32im (LO7 $val), 0)>;
1490+
def : Pat<(i32 simm7:$val), (EXTRACT_SUBREG (ORim (LO7 $val), 0), sub_i32)>;
14991491
def : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>;
15001492
// Medium immediates.
1501-
def : Pat<(i32 simm32:$val), (LEA32zii 0, 0, (LO32 $val))>;
1493+
def : Pat<(i32 simm32:$val),
1494+
(EXTRACT_SUBREG (LEAzii 0, 0, (LO32 $val)), sub_i32)>;
15021495
def : Pat<(i64 simm32:$val), (LEAzii 0, 0, (LO32 $val))>;
15031496
def : Pat<(i64 uimm32:$val), (ANDrm (LEAzii 0, 0, (LO32 $val)), !add(32, 64))>;
15041497
// Arbitrary immediates.
@@ -1539,8 +1532,8 @@ def : Pat<(sext_inreg I64:$src, i8),
15391532
(SRALri (SLLri $src, 56), 56)>;
15401533
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),
15411534
(EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;
1542-
def : Pat<(and (trunc i64:$src), 0xff),
1543-
(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>;
1535+
def : Pat<(i32 (and (trunc i64:$src), 0xff)),
1536+
(EXTRACT_SUBREG (ANDrm $src, !add(56, 64)), sub_i32)>;
15441537

15451538
// Cast to i16
15461539
def : Pat<(sext_inreg I32:$src, i16),
@@ -1549,8 +1542,8 @@ def : Pat<(sext_inreg I64:$src, i16),
15491542
(SRALri (SLLri $src, 48), 48)>;
15501543
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),
15511544
(EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;
1552-
def : Pat<(and (trunc i64:$src), 0xffff),
1553-
(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>;
1545+
def : Pat<(i32 (and (trunc i64:$src), 0xffff)),
1546+
(EXTRACT_SUBREG (ANDrm $src, !add(48, 64)), sub_i32)>;
15541547

15551548
// Cast to i32
15561549
def : Pat<(i32 (trunc i64:$src)),
@@ -1995,11 +1988,20 @@ def : Pat<(f32 (bitconvert i32:$op)),
19951988
(EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
19961989
$op, sub_i32), 32), sub_f32)>;
19971990

1998-
// Several special pattern matches to optimize code
1991+
// Optimize code A generated by `(unsigned char)c << 5` to B.
1992+
// A) sla.w.sx %s0, %s0, 5
1993+
// lea %s1, 224 ; 0xE0
1994+
// and %s0, %s0, %s1
1995+
// B) sla.w.sx %s0, %s0, 5
1996+
// and %s0, %s0, (56)0
19991997

2000-
def : Pat<(i32 (and i32:$lhs, 0xff)),
2001-
(AND32rm $lhs, !add(56, 64))>;
2002-
def : Pat<(i32 (and i32:$lhs, 0xffff)),
2003-
(AND32rm $lhs, !add(48, 64))>;
2004-
def : Pat<(i32 (and i32:$lhs, 0xffffffff)),
2005-
(AND32rm $lhs, !add(32, 64))>;
1998+
def : Pat<(i32 (and i32:$val, 0xff)),
1999+
(EXTRACT_SUBREG
2000+
(ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
2001+
!add(56, 64)), sub_i32)>;
2002+
def : Pat<(i32 (and i32:$val, 0xffff)),
2003+
(EXTRACT_SUBREG
2004+
(ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
2005+
!add(48, 64)), sub_i32)>;
2006+
def : Pat<(i64 (and i64:$val, 0xffffffff)),
2007+
(ANDrm $val, !add(32, 64))>;

‎llvm/test/CodeGen/VE/cttz.ll

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,9 @@ define i64 @func64(i64 %p) {
3939
define signext i32 @func32s(i32 signext %p) {
4040
; CHECK-LABEL: func32s:
4141
; CHECK: .LBB{{[0-9]+}}_2:
42-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
4342
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
44-
; CHECK-NEXT: xor %s0, -1, %s0
45-
; CHECK-NEXT: and %s0, %s0, %s1
46-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
43+
; CHECK-NEXT: nnd %s0, %s0, %s1
44+
; CHECK-NEXT: and %s0, %s0, (32)0
4745
; CHECK-NEXT: pcnt %s0, %s0
4846
; CHECK-NEXT: or %s11, 0, %s9
4947
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
@@ -53,11 +51,9 @@ define signext i32 @func32s(i32 signext %p) {
5351
define zeroext i32 @func32z(i32 zeroext %p) {
5452
; CHECK-LABEL: func32z:
5553
; CHECK: .LBB{{[0-9]+}}_2:
56-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
5754
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
58-
; CHECK-NEXT: xor %s0, -1, %s0
59-
; CHECK-NEXT: and %s0, %s0, %s1
60-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
55+
; CHECK-NEXT: nnd %s0, %s0, %s1
56+
; CHECK-NEXT: and %s0, %s0, (32)0
6157
; CHECK-NEXT: pcnt %s0, %s0
6258
; CHECK-NEXT: or %s11, 0, %s9
6359
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
@@ -67,11 +63,9 @@ define zeroext i32 @func32z(i32 zeroext %p) {
6763
define signext i16 @func16s(i16 signext %p) {
6864
; CHECK-LABEL: func16s:
6965
; CHECK: .LBB{{[0-9]+}}_2:
70-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
7166
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
72-
; CHECK-NEXT: xor %s0, -1, %s0
73-
; CHECK-NEXT: and %s0, %s0, %s1
74-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
67+
; CHECK-NEXT: nnd %s0, %s0, %s1
68+
; CHECK-NEXT: and %s0, %s0, (32)0
7569
; CHECK-NEXT: pcnt %s0, %s0
7670
; CHECK-NEXT: or %s11, 0, %s9
7771
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
@@ -81,11 +75,9 @@ define signext i16 @func16s(i16 signext %p) {
8175
define zeroext i16 @func16z(i16 zeroext %p) {
8276
; CHECK-LABEL: func16z:
8377
; CHECK: .LBB{{[0-9]+}}_2:
84-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
8578
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
86-
; CHECK-NEXT: xor %s0, -1, %s0
87-
; CHECK-NEXT: and %s0, %s0, %s1
88-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
79+
; CHECK-NEXT: nnd %s0, %s0, %s1
80+
; CHECK-NEXT: and %s0, %s0, (32)0
8981
; CHECK-NEXT: pcnt %s0, %s0
9082
; CHECK-NEXT: or %s11, 0, %s9
9183
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
@@ -95,11 +87,9 @@ define zeroext i16 @func16z(i16 zeroext %p) {
9587
define signext i8 @func8s(i8 signext %p) {
9688
; CHECK-LABEL: func8s:
9789
; CHECK: .LBB{{[0-9]+}}_2:
98-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
9990
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
100-
; CHECK-NEXT: xor %s0, -1, %s0
101-
; CHECK-NEXT: and %s0, %s0, %s1
102-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
91+
; CHECK-NEXT: nnd %s0, %s0, %s1
92+
; CHECK-NEXT: and %s0, %s0, (32)0
10393
; CHECK-NEXT: pcnt %s0, %s0
10494
; CHECK-NEXT: or %s11, 0, %s9
10595
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
@@ -109,11 +99,9 @@ define signext i8 @func8s(i8 signext %p) {
10999
define zeroext i8 @func8z(i8 zeroext %p) {
110100
; CHECK-LABEL: func8z:
111101
; CHECK: .LBB{{[0-9]+}}_2:
112-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
113102
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
114-
; CHECK-NEXT: xor %s0, -1, %s0
115-
; CHECK-NEXT: and %s0, %s0, %s1
116-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
103+
; CHECK-NEXT: nnd %s0, %s0, %s1
104+
; CHECK-NEXT: and %s0, %s0, (32)0
117105
; CHECK-NEXT: pcnt %s0, %s0
118106
; CHECK-NEXT: or %s11, 0, %s9
119107
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)

‎llvm/test/CodeGen/VE/nnd.ll

Lines changed: 12 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,7 @@
33
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
44
; CHECK-LABEL: func8s:
55
; CHECK: .LBB{{[0-9]+}}_2:
6-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
7-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
8-
; CHECK-NEXT: xor %s0, -1, %s0
9-
; CHECK-NEXT: and %s0, %s0, %s1
10-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
6+
; CHECK-NEXT: nnd %s0, %s0, %s1
117
; CHECK-NEXT: or %s11, 0, %s9
128
%not = xor i8 %a, -1
139
%res = and i8 %not, %b
@@ -17,11 +13,7 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) {
1713
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
1814
; CHECK-LABEL: func8z:
1915
; CHECK: .LBB{{[0-9]+}}_2:
20-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
21-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
22-
; CHECK-NEXT: xor %s0, -1, %s0
23-
; CHECK-NEXT: and %s0, %s1, %s0
24-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
16+
; CHECK-NEXT: nnd %s0, %s0, %s1
2517
; CHECK-NEXT: or %s11, 0, %s9
2618
%not = xor i8 %a, -1
2719
%res = and i8 %b, %not
@@ -31,10 +23,8 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
3123
define signext i8 @funci8s(i8 signext %a) {
3224
; CHECK-LABEL: funci8s:
3325
; CHECK: .LBB{{[0-9]+}}_2:
34-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
35-
; CHECK-NEXT: xor %s0, -1, %s0
36-
; CHECK-NEXT: and %s0, 5, %s0
37-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
26+
; CHECK-NEXT: or %s1, 5, (0)1
27+
; CHECK-NEXT: nnd %s0, %s0, %s1
3828
; CHECK-NEXT: or %s11, 0, %s9
3929
%not = xor i8 %a, -1
4030
%res = and i8 %not, 5
@@ -44,10 +34,8 @@ define signext i8 @funci8s(i8 signext %a) {
4434
define zeroext i8 @funci8z(i8 zeroext %a) {
4535
; CHECK-LABEL: funci8z:
4636
; CHECK: .LBB{{[0-9]+}}_2:
47-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
48-
; CHECK-NEXT: xor %s0, -1, %s0
4937
; CHECK-NEXT: lea %s1, 251
50-
; CHECK-NEXT: and %s0, %s0, %s1
38+
; CHECK-NEXT: nnd %s0, %s0, %s1
5139
; CHECK-NEXT: or %s11, 0, %s9
5240
%not = xor i8 %a, -1
5341
%res = and i8 -5, %not
@@ -57,11 +45,7 @@ define zeroext i8 @funci8z(i8 zeroext %a) {
5745
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
5846
; CHECK-LABEL: func16s:
5947
; CHECK: .LBB{{[0-9]+}}_2:
60-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
61-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
62-
; CHECK-NEXT: xor %s0, -1, %s0
63-
; CHECK-NEXT: and %s0, %s0, %s1
64-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
48+
; CHECK-NEXT: nnd %s0, %s0, %s1
6549
; CHECK-NEXT: or %s11, 0, %s9
6650
%not = xor i16 %a, -1
6751
%res = and i16 %not, %b
@@ -71,11 +55,7 @@ define signext i16 @func16s(i16 signext %a, i16 signext %b) {
7155
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
7256
; CHECK-LABEL: func16z:
7357
; CHECK: .LBB{{[0-9]+}}_2:
74-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
75-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
76-
; CHECK-NEXT: xor %s0, -1, %s0
77-
; CHECK-NEXT: and %s0, %s1, %s0
78-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
58+
; CHECK-NEXT: nnd %s0, %s0, %s1
7959
; CHECK-NEXT: or %s11, 0, %s9
8060
%not = xor i16 %a, -1
8161
%res = and i16 %b, %not
@@ -85,9 +65,7 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
8565
define signext i16 @funci16s(i16 signext %a) {
8666
; CHECK-LABEL: funci16s:
8767
; CHECK: .LBB{{[0-9]+}}_2:
88-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
8968
; CHECK-NEXT: xor %s0, -1, %s0
90-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
9169
; CHECK-NEXT: or %s11, 0, %s9
9270
%not = xor i16 %a, -1
9371
%res = and i16 %not, 65535
@@ -97,10 +75,7 @@ define signext i16 @funci16s(i16 signext %a) {
9775
define zeroext i16 @funci16z(i16 zeroext %a) {
9876
; CHECK-LABEL: funci16z:
9977
; CHECK: .LBB{{[0-9]+}}_2:
100-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
101-
; CHECK-NEXT: xor %s0, -1, %s0
102-
; CHECK-NEXT: and %s0, %s0, (52)0
103-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
78+
; CHECK-NEXT: nnd %s0, %s0, (52)0
10479
; CHECK-NEXT: or %s11, 0, %s9
10580
%not = xor i16 %a, -1
10681
%res = and i16 4095, %not
@@ -110,11 +85,7 @@ define zeroext i16 @funci16z(i16 zeroext %a) {
11085
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
11186
; CHECK-LABEL: func32s:
11287
; CHECK: .LBB{{[0-9]+}}_2:
113-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
114-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
115-
; CHECK-NEXT: xor %s0, -1, %s0
116-
; CHECK-NEXT: and %s0, %s0, %s1
117-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
88+
; CHECK-NEXT: nnd %s0, %s0, %s1
11889
; CHECK-NEXT: or %s11, 0, %s9
11990
%not = xor i32 %a, -1
12091
%res = and i32 %not, %b
@@ -124,11 +95,7 @@ define signext i32 @func32s(i32 signext %a, i32 signext %b) {
12495
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
12596
; CHECK-LABEL: func32z:
12697
; CHECK: .LBB{{[0-9]+}}_2:
127-
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
128-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
129-
; CHECK-NEXT: xor %s0, -1, %s0
130-
; CHECK-NEXT: and %s0, %s0, %s1
131-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
98+
; CHECK-NEXT: nnd %s0, %s0, %s1
13299
; CHECK-NEXT: or %s11, 0, %s9
133100
%not = xor i32 %a, -1
134101
%res = and i32 %not, %b
@@ -138,10 +105,7 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
138105
define signext i32 @funci32s(i32 signext %a) {
139106
; CHECK-LABEL: funci32s:
140107
; CHECK: .LBB{{[0-9]+}}_2:
141-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
142-
; CHECK-NEXT: xor %s0, -1, %s0
143-
; CHECK-NEXT: and %s0, %s0, (36)0
144-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
108+
; CHECK-NEXT: nnd %s0, %s0, (36)0
145109
; CHECK-NEXT: or %s11, 0, %s9
146110
%not = xor i32 %a, -1
147111
%res = and i32 %not, 268435455
@@ -151,10 +115,7 @@ define signext i32 @funci32s(i32 signext %a) {
151115
define zeroext i32 @funci32z(i32 zeroext %a) {
152116
; CHECK-LABEL: funci32z:
153117
; CHECK: .LBB{{[0-9]+}}_2:
154-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
155-
; CHECK-NEXT: xor %s0, -1, %s0
156-
; CHECK-NEXT: and %s0, %s0, (36)0
157-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
118+
; CHECK-NEXT: nnd %s0, %s0, (36)0
158119
; CHECK-NEXT: or %s11, 0, %s9
159120
%not = xor i32 %a, -1
160121
%res = and i32 %not, 268435455

‎llvm/test/CodeGen/VE/or.ll

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,7 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
2121
define signext i8 @funci8s(i8 signext %a) {
2222
; CHECK-LABEL: funci8s:
2323
; CHECK: .LBB{{[0-9]+}}_2:
24-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
2524
; CHECK-NEXT: or %s0, 5, %s0
26-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
2725
; CHECK-NEXT: or %s11, 0, %s9
2826
%res = or i8 %a, 5
2927
ret i8 %res
@@ -32,10 +30,8 @@ define signext i8 @funci8s(i8 signext %a) {
3230
define zeroext i8 @funci8z(i8 zeroext %a) {
3331
; CHECK-LABEL: funci8z:
3432
; CHECK: .LBB{{[0-9]+}}_2:
35-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
3633
; CHECK-NEXT: lea %s1, 251
3734
; CHECK-NEXT: or %s0, %s0, %s1
38-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
3935
; CHECK-NEXT: or %s11, 0, %s9
4036
%res = or i8 -5, %a
4137
ret i8 %res
@@ -71,9 +67,7 @@ define signext i16 @funci16s(i16 signext %a) {
7167
define zeroext i16 @funci16z(i16 zeroext %a) {
7268
; CHECK-LABEL: funci16z:
7369
; CHECK: .LBB{{[0-9]+}}_2:
74-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
7570
; CHECK-NEXT: or %s0, %s0, (52)0
76-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
7771
; CHECK-NEXT: or %s11, 0, %s9
7872
%res = or i16 4095, %a
7973
ret i16 %res
@@ -100,9 +94,7 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
10094
define signext i32 @funci32s(i32 signext %a) {
10195
; CHECK-LABEL: funci32s:
10296
; CHECK: .LBB{{[0-9]+}}_2:
103-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
10497
; CHECK-NEXT: or %s0, %s0, (36)0
105-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
10698
; CHECK-NEXT: or %s11, 0, %s9
10799
%res = or i32 %a, 268435455
108100
ret i32 %res
@@ -111,9 +103,7 @@ define signext i32 @funci32s(i32 signext %a) {
111103
define zeroext i32 @funci32z(i32 zeroext %a) {
112104
; CHECK-LABEL: funci32z:
113105
; CHECK: .LBB{{[0-9]+}}_2:
114-
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
115106
; CHECK-NEXT: or %s0, %s0, (36)0
116-
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
117107
; CHECK-NEXT: or %s11, 0, %s9
118108
%res = or i32 %a, 268435455
119109
ret i32 %res

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