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arsenmarsenm
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GlobalISel: Add basic legalization for G_BITREVERSE
llvm-svn: 370979
1 parent 56e9b60 commit 5ff310e

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3 files changed

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3 files changed

+177
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‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1470,6 +1470,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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Observer.changedInstr(MI);
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return Legalized;
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}
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case TargetOpcode::G_BITREVERSE: {
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Observer.changingInstr(MI);
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Register DstReg = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(DstReg);
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unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
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Register DstExt = MRI.createGenericVirtualRegister(WideTy);
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widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
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MI.getOperand(0).setReg(DstExt);
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
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auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
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auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
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MIRBuilder.buildTrunc(DstReg, Shift);
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Observer.changedInstr(MI);
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return Legalized;
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}
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_MUL:
@@ -2826,6 +2844,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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case G_FSIN:
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case G_FSQRT:
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case G_BSWAP:
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case G_BITREVERSE:
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case G_SDIV:
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case G_SMIN:
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case G_SMAX:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -433,7 +433,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.widenScalarToNextPow2(1, 32);
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// TODO: Expand for > s32
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getActionDefinitionsBuilder(G_BSWAP)
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getActionDefinitionsBuilder({G_BSWAP, G_BITREVERSE})
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.legalFor({S32})
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.clampScalar(0, S32, S32)
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.scalarize(0);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir

Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,157 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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---
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name: bitreverse_s8
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_s8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: $vgpr0 = COPY [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s8) = G_TRUNC %0
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%2:_(s8) = G_BITREVERSE %1
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%3:_(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: bitreverse_s16
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: $vgpr0 = COPY [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_BITREVERSE %1
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%3:_(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: bitreverse_s24
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_s24
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: $vgpr0 = COPY [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s24) = G_TRUNC %0
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%2:_(s24) = G_BITREVERSE %1
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%3:_(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: bitreverse_s32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
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; CHECK: $vgpr0 = COPY [[BITREVERSE]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_BITREVERSE %0
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$vgpr0 = COPY %1
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...
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---
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name: bitreverse_v2s16
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
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; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY2]]
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; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE1]], [[C]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
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; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = G_BITREVERSE %0
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$vgpr0 = COPY %1
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...
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---
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name: bitreverse_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: bitreverse_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV1]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITREVERSE]](s32), [[BITREVERSE1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = G_BITREVERSE %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: bitreverse_s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: bitreverse_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[COPY]]
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; CHECK: $vgpr0_vgpr1 = COPY [[BITREVERSE]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_BITREVERSE %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: bitreverse_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: bitreverse_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV1]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[BITREVERSE]](s64), [[BITREVERSE1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s64>) = G_BITREVERSE %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...

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