We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 1c604a9 commit 61b3106Copy full SHA for 61b3106
llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -28,7 +28,6 @@ def SIEncodingFamily {
28
int GFX9 = 5;
29
int GFX10 = 6;
30
int SDWA10 = 7;
31
- int GFX10_B = 8;
32
}
33
34
//===----------------------------------------------------------------------===//
@@ -2500,8 +2499,7 @@ def getMCOpcodeGen : InstrMapping {
2500
2499
[!cast<string>(SIEncodingFamily.GFX80)],
2501
[!cast<string>(SIEncodingFamily.GFX9)],
2502
[!cast<string>(SIEncodingFamily.GFX10)],
2503
- [!cast<string>(SIEncodingFamily.SDWA10)],
2504
- [!cast<string>(SIEncodingFamily.GFX10_B)]];
+ [!cast<string>(SIEncodingFamily.SDWA10)]];
2505
2506
2507
// Get equivalent SOPK instruction.
0 commit comments