[RISCV][GISel] Add widenScalarToNextPow2 to G_SEXTLOAD/G_ZEXTLOAD legalization.

This fixes i8->i48 on RV64.

Author: topperc

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -120,6 +120,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
   if (XLen == 64)
     ExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
   ExtLoadActions
+    .widenScalarToNextPow2(0)
     .clampScalar(0, s32, XLenLLT)
     .lower();
 

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir

@@ -121,6 +121,26 @@ body:             |
     $x10 = COPY %2(s64)
     PseudoRET implicit $x10
 
+...
+---
+name:            zextload_i8_i48
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: zextload_i8_i48
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %2:_(s48) = G_ZEXTLOAD %0(p0) :: (load (s8))
+    %3:_(s64) = G_ANYEXT %2(s48)
+    $x10 = COPY %3(s64)
+    PseudoRET implicit $x10
+
 ...
 ---
 name:            sextload_i8_i16
@@ -242,3 +262,24 @@ body:             |
     PseudoRET implicit $x10
 
 ...
+---
+name:            sextload_i8_i48
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: sextload_i8_i48
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %2:_(s48) = G_SEXTLOAD %0(p0) :: (load (s8))
+    %3:_(s64) = G_ANYEXT %2(s48)
+    $x10 = COPY %3(s64)
+    PseudoRET implicit $x10
+
+...