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[ARM] Added more patterns to generate SSAT/USAT with shift
Added patterns to generate an SSAT or USAT with shift for SSAT/USAT instructions that are matched from IR patterns. Differential Revision: https://reviews.llvm.org/D88145
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-20
lines changed

5 files changed

+85
-20
lines changed

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -167,9 +167,9 @@ def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
167167
[SDNPInGlue]>;
168168
def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>;
169169

170-
def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
170+
def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
171171

172-
def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;
172+
def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;
173173

174174
def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
175175
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
@@ -4082,9 +4082,9 @@ def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
40824082
(SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
40834083
def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
40844084
(USAT imm0_31:$pos, GPRnopc:$a, 0)>;
4085-
def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
4085+
def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
40864086
(SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
4087-
def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
4087+
def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
40884088
(USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
40894089
def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos),
40904090
(SSAT16 imm1_16:$pos, GPRnopc:$a)>;
@@ -4098,6 +4098,14 @@ def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
40984098
(USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
40994099
def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
41004100
(USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
4101+
def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4102+
(SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4103+
def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4104+
(SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
4105+
def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4106+
(USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4107+
def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4108+
(USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
41014109

41024110

41034111
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2624,9 +2624,9 @@ def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),
26242624
let Inst{4} = 0;
26252625
}
26262626

2627-
def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2627+
def : T2Pat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
26282628
(t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2629-
def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
2629+
def : T2Pat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
26302630
(t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
26312631
def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),
26322632
(t2SSAT imm1_32:$pos, GPR:$a, 0)>;
@@ -2644,6 +2644,14 @@ def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
26442644
(t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
26452645
def : T2Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
26462646
(t2USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
2647+
def : T2Pat<(ARMssat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
2648+
(t2SSAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
2649+
def : T2Pat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
2650+
(t2SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
2651+
def : T2Pat<(ARMusat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
2652+
(t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
2653+
def : T2Pat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
2654+
(t2USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
26472655

26482656

26492657
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/ARM/ssat-with-shift.ll

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,32 @@ entry:
2424
ret i32 %0
2525
}
2626

27+
define arm_aapcs_vfpcc i32 @ssat_lsl2(i32 %num){
28+
; CHECK-LABEL: ssat_lsl2:
29+
; CHECK: @ %bb.0: @ %entry
30+
; CHECK-NEXT: ssat r0, #16, r0, lsl #15
31+
; CHECK-NEXT: bx lr
32+
entry:
33+
%shl = shl nsw i32 %num, 15
34+
%0 = icmp sgt i32 %shl, -32768
35+
%1 = select i1 %0, i32 %shl, i32 -32768
36+
%2 = icmp slt i32 %1, 32767
37+
%3 = select i1 %2, i32 %1, i32 32767
38+
ret i32 %3
39+
}
40+
41+
define arm_aapcs_vfpcc i32 @ssat_asr2(i32 %num){
42+
; CHECK-LABEL: ssat_asr2:
43+
; CHECK: @ %bb.0: @ %entry
44+
; CHECK-NEXT: ssat r0, #16, r0, asr #15
45+
; CHECK-NEXT: bx lr
46+
entry:
47+
%shr = ashr i32 %num, 15
48+
%0 = icmp sgt i32 %shr, -32768
49+
%1 = select i1 %0, i32 %shr, i32 -32768
50+
%2 = icmp slt i32 %1, 32767
51+
%3 = select i1 %2, i32 %1, i32 32767
52+
ret i32 %3
53+
}
54+
2755
declare i32 @llvm.arm.ssat(i32, i32)

‎llvm/test/CodeGen/ARM/usat-with-shift.ll

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,32 @@ entry:
2424
ret i32 %0
2525
}
2626

27+
define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
28+
; CHECK-LABEL: usat_lsl2:
29+
; CHECK: @ %bb.0: @ %entry
30+
; CHECK-NEXT: usat r0, #15, r0, lsl #15
31+
; CHECK-NEXT: bx lr
32+
entry:
33+
%shl = shl nsw i32 %num, 15
34+
%0 = icmp sgt i32 %shl, 0
35+
%1 = select i1 %0, i32 %shl, i32 0
36+
%2 = icmp slt i32 %1, 32767
37+
%3 = select i1 %2, i32 %1, i32 32767
38+
ret i32 %3
39+
}
40+
41+
define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
42+
; CHECK-LABEL: usat_asr2:
43+
; CHECK: @ %bb.0: @ %entry
44+
; CHECK-NEXT: usat r0, #15, r0, asr #15
45+
; CHECK-NEXT: bx lr
46+
entry:
47+
%shr = ashr i32 %num, 15
48+
%0 = icmp sgt i32 %shr, 0
49+
%1 = select i1 %0, i32 %shr, i32 0
50+
%2 = icmp slt i32 %1, 32767
51+
%3 = select i1 %2, i32 %1, i32 32767
52+
ret i32 %3
53+
}
54+
2755
declare i32 @llvm.arm.usat(i32, i32)

‎llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1145,8 +1145,7 @@ define arm_aapcs_vfpcc void @ssatmul_4_q15(i16* nocapture readonly %pSrcA, i16*
11451145
; CHECK-NEXT: ldrsh r0, [r12], #2
11461146
; CHECK-NEXT: ldrsh r1, [r6], #2
11471147
; CHECK-NEXT: muls r0, r1, r0
1148-
; CHECK-NEXT: asrs r0, r0, #15
1149-
; CHECK-NEXT: ssat r0, #16, r0
1148+
; CHECK-NEXT: ssat r0, #16, r0, asr #15
11501149
; CHECK-NEXT: strh r0, [r4], #2
11511150
; CHECK-NEXT: le lr, .LBB5_7
11521151
; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup
@@ -1279,8 +1278,7 @@ define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16*
12791278
; CHECK-NEXT: ldrsh r0, [r12], #2
12801279
; CHECK-NEXT: ldrsh r1, [r6], #2
12811280
; CHECK-NEXT: muls r0, r1, r0
1282-
; CHECK-NEXT: asrs r0, r0, #15
1283-
; CHECK-NEXT: ssat r0, #16, r0
1281+
; CHECK-NEXT: ssat r0, #16, r0, asr #15
12841282
; CHECK-NEXT: strh r0, [r4], #2
12851283
; CHECK-NEXT: le lr, .LBB6_7
12861284
; CHECK-NEXT: .LBB6_8: @ %for.cond.cleanup
@@ -1410,8 +1408,7 @@ define arm_aapcs_vfpcc void @ssatmul_8i_q15(i16* nocapture readonly %pSrcA, i16*
14101408
; CHECK-NEXT: ldrsh r0, [r12], #2
14111409
; CHECK-NEXT: ldrsh r1, [r6], #2
14121410
; CHECK-NEXT: muls r0, r1, r0
1413-
; CHECK-NEXT: asrs r0, r0, #15
1414-
; CHECK-NEXT: ssat r0, #16, r0
1411+
; CHECK-NEXT: ssat r0, #16, r0, asr #15
14151412
; CHECK-NEXT: strh r0, [r4], #2
14161413
; CHECK-NEXT: le lr, .LBB7_7
14171414
; CHECK-NEXT: .LBB7_8: @ %for.cond.cleanup
@@ -2218,8 +2215,7 @@ define arm_aapcs_vfpcc void @ssatmul_4_q7(i8* nocapture readonly %pSrcA, i8* noc
22182215
; CHECK-NEXT: ldrsb r0, [r12], #1
22192216
; CHECK-NEXT: ldrsb r1, [r6], #1
22202217
; CHECK-NEXT: muls r0, r1, r0
2221-
; CHECK-NEXT: asrs r0, r0, #7
2222-
; CHECK-NEXT: ssat r0, #8, r0
2218+
; CHECK-NEXT: ssat r0, #8, r0, asr #7
22232219
; CHECK-NEXT: strb r0, [r4], #1
22242220
; CHECK-NEXT: le lr, .LBB13_7
22252221
; CHECK-NEXT: .LBB13_8: @ %for.cond.cleanup
@@ -2346,8 +2342,7 @@ define arm_aapcs_vfpcc void @ssatmul_8_q7(i8* nocapture readonly %pSrcA, i8* noc
23462342
; CHECK-NEXT: ldrsb r0, [r12], #1
23472343
; CHECK-NEXT: ldrsb r1, [r6], #1
23482344
; CHECK-NEXT: muls r0, r1, r0
2349-
; CHECK-NEXT: asrs r0, r0, #7
2350-
; CHECK-NEXT: ssat r0, #8, r0
2345+
; CHECK-NEXT: ssat r0, #8, r0, asr #7
23512346
; CHECK-NEXT: strb r0, [r4], #1
23522347
; CHECK-NEXT: le lr, .LBB14_7
23532348
; CHECK-NEXT: .LBB14_8: @ %for.cond.cleanup
@@ -2480,8 +2475,7 @@ define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no
24802475
; CHECK-NEXT: ldrsb r0, [r12], #1
24812476
; CHECK-NEXT: ldrsb r1, [r6], #1
24822477
; CHECK-NEXT: muls r0, r1, r0
2483-
; CHECK-NEXT: asrs r0, r0, #7
2484-
; CHECK-NEXT: ssat r0, #8, r0
2478+
; CHECK-NEXT: ssat r0, #8, r0, asr #7
24852479
; CHECK-NEXT: strb r0, [r4], #1
24862480
; CHECK-NEXT: le lr, .LBB15_7
24872481
; CHECK-NEXT: .LBB15_8: @ %for.cond.cleanup
@@ -2611,8 +2605,7 @@ define arm_aapcs_vfpcc void @ssatmul_16i_q7(i8* nocapture readonly %pSrcA, i8* n
26112605
; CHECK-NEXT: ldrsb r0, [r12], #1
26122606
; CHECK-NEXT: ldrsb r1, [r6], #1
26132607
; CHECK-NEXT: muls r0, r1, r0
2614-
; CHECK-NEXT: asrs r0, r0, #7
2615-
; CHECK-NEXT: ssat r0, #8, r0
2608+
; CHECK-NEXT: ssat r0, #8, r0, asr #7
26162609
; CHECK-NEXT: strb r0, [r4], #1
26172610
; CHECK-NEXT: le lr, .LBB16_7
26182611
; CHECK-NEXT: .LBB16_8: @ %for.cond.cleanup

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