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[X86][GlobalISel] Replace a misuse of SUBREG_TO_REG with INSERT_SUBREG.
SUBREG_TO_REG is supposed to be used when we know the producing instruction already zeroed the bits we're extending. But that's not the case here. So INSERT_SUBREG with an IMPLICIT_DEF is the correct thing to use.
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+50
-31
lines changed

3 files changed

+50
-31
lines changed

‎llvm/lib/Target/X86/X86InstructionSelector.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -808,12 +808,17 @@ bool X86InstructionSelector::selectZext(MachineInstr &I,
808808
else
809809
return false;
810810

811-
unsigned DefReg = SrcReg;
811+
Register DefReg = SrcReg;
812812
if (DstTy != LLT::scalar(8)) {
813+
Register ImpDefReg =
814+
MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
815+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
816+
TII.get(TargetOpcode::IMPLICIT_DEF), ImpDefReg);
817+
813818
DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
814819
BuildMI(*I.getParent(), I, I.getDebugLoc(),
815-
TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
816-
.addImm(0)
820+
TII.get(TargetOpcode::INSERT_SUBREG), DefReg)
821+
.addReg(ImpDefReg)
817822
.addReg(SrcReg)
818823
.addImm(X86::sub_8bit);
819824
}

‎llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

Lines changed: 39 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,9 @@ body: |
100100
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
101101
; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
102102
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
103-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
104-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
103+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
104+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
105+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
105106
; CHECK: $eax = COPY [[AND32ri8_]]
106107
; CHECK: RET 0, implicit $eax
107108
%0(s8) = COPY $dil
@@ -131,8 +132,9 @@ body: |
131132
; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
132133
; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
133134
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
134-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
135-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
135+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
136+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
137+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
136138
; CHECK: $eax = COPY [[AND32ri8_]]
137139
; CHECK: RET 0, implicit $eax
138140
%0(s16) = COPY $di
@@ -162,8 +164,9 @@ body: |
162164
; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
163165
; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
164166
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
165-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
166-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
167+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
168+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
169+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
167170
; CHECK: $eax = COPY [[AND32ri8_]]
168171
; CHECK: RET 0, implicit $eax
169172
%0(s64) = COPY $rdi
@@ -193,8 +196,9 @@ body: |
193196
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
194197
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
195198
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
196-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
197-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
199+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
200+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
201+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
198202
; CHECK: $eax = COPY [[AND32ri8_]]
199203
; CHECK: RET 0, implicit $eax
200204
%0(s32) = COPY $edi
@@ -224,8 +228,9 @@ body: |
224228
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
225229
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
226230
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
227-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
228-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
231+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
232+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
233+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
229234
; CHECK: $eax = COPY [[AND32ri8_]]
230235
; CHECK: RET 0, implicit $eax
231236
%0(s32) = COPY $edi
@@ -255,8 +260,9 @@ body: |
255260
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
256261
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
257262
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
258-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
259-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
263+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
264+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
265+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
260266
; CHECK: $eax = COPY [[AND32ri8_]]
261267
; CHECK: RET 0, implicit $eax
262268
%0(s32) = COPY $edi
@@ -286,8 +292,9 @@ body: |
286292
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
287293
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
288294
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
289-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
290-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
295+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
296+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
297+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
291298
; CHECK: $eax = COPY [[AND32ri8_]]
292299
; CHECK: RET 0, implicit $eax
293300
%0(s32) = COPY $edi
@@ -317,8 +324,9 @@ body: |
317324
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
318325
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
319326
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
320-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
321-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
327+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
328+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
329+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
322330
; CHECK: $eax = COPY [[AND32ri8_]]
323331
; CHECK: RET 0, implicit $eax
324332
%0(s32) = COPY $edi
@@ -348,8 +356,9 @@ body: |
348356
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
349357
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
350358
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
351-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
352-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
359+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
360+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
361+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
353362
; CHECK: $eax = COPY [[AND32ri8_]]
354363
; CHECK: RET 0, implicit $eax
355364
%0(s32) = COPY $edi
@@ -379,8 +388,9 @@ body: |
379388
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
380389
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
381390
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
382-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
383-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
391+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
392+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
393+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
384394
; CHECK: $eax = COPY [[AND32ri8_]]
385395
; CHECK: RET 0, implicit $eax
386396
%0(s32) = COPY $edi
@@ -410,8 +420,9 @@ body: |
410420
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
411421
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
412422
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
413-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
414-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
423+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
424+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
425+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
415426
; CHECK: $eax = COPY [[AND32ri8_]]
416427
; CHECK: RET 0, implicit $eax
417428
%0(s32) = COPY $edi
@@ -441,8 +452,9 @@ body: |
441452
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
442453
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
443454
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
444-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
445-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
455+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
456+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
457+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
446458
; CHECK: $eax = COPY [[AND32ri8_]]
447459
; CHECK: RET 0, implicit $eax
448460
%0(s32) = COPY $edi
@@ -472,8 +484,9 @@ body: |
472484
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
473485
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
474486
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
475-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
476-
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
487+
; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
488+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
489+
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
477490
; CHECK: $eax = COPY [[AND32ri8_]]
478491
; CHECK: RET 0, implicit $eax
479492
%0(s32) = COPY $edi

‎llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,9 @@ body: |
3838
3939
; ALL-LABEL: name: test_zext_i1
4040
; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
41-
; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit
42-
; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
41+
; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
42+
; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit
43+
; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
4344
; ALL: $rax = COPY [[AND64ri8_]]
4445
; ALL: RET 0, implicit $rax
4546
%0(s8) = COPY $dil

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