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[RISCV] add the assemble and disassemble support of Zvlsseg instructions
This implements the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.9 spec version. Reviewed by HsiangKai Differential Revision: https://reviews.llvm.org/D84416
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‎llvm/lib/Target/RISCV/RISCV.td

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@@ -155,6 +155,14 @@ def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
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AssemblerPredicate<(all_of FeatureStdExtV),
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"'V' (Vector Instructions)">;
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def FeatureStdExtZvlsseg
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: SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
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"'Zvlsseg' (Vector segment load/store instructions)",
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[FeatureStdExtV]>;
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def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
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AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
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"'Zvlsseg' (Vector segment load/store instructions)">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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def IsRV64 : Predicate<"Subtarget->is64Bit()">,

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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Original file line numberDiff line numberDiff line change
@@ -124,6 +124,27 @@ class VWholeLoad<bits<3> nf, string opcodestr>
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let vm = 1;
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let Uses = [];
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}
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// segment load vd, (rs1), vm
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class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop,
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RISCVWidth width, string opcodestr>
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: RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0},
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(outs VRegOp:$vd),
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(ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
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// segment load vd, (rs1), rs2, vm
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class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVLS<nf, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $rs2$vm">;
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// segment load vd, (rs1), vs2, vm
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class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVLX<nf, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $vs2$vm">;
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} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
@@ -154,6 +175,24 @@ class VWholeStore<bits<3> nf, string opcodestr>
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let vm = 1;
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let Uses = [];
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}
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// segment store vd, vs3, (rs1), vm
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class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
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(outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
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"$vs3, (${rs1})$vm">;
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// segment store vd, vs3, (rs1), rs2, vm
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class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $rs2$vm">;
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// segment store vd, vs3, (rs1), vs2, vm
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class VIndexedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $vs2$vm">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
@@ -913,3 +952,72 @@ foreach nf = [1, 2, 4, 8] in {
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}
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtZvlsseg] in {
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foreach nf=2-8 in {
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def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">;
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def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">;
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def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">;
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def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">;
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def VLSEG#nf#E128_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth128, "vlseg"#nf#"e128.v">;
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def VLSEG#nf#E256_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth256, "vlseg"#nf#"e256.v">;
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def VLSEG#nf#E512_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth512, "vlseg"#nf#"e512.v">;
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def VLSEG#nf#E1024_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth1024, "vlseg"#nf#"e1024.v">;
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def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">;
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def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">;
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def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth32, "vlseg"#nf#"e32ff.v">;
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def VLSEG#nf#E64FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth64, "vlseg"#nf#"e64ff.v">;
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def VLSEG#nf#E128FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth128, "vlseg"#nf#"e128ff.v">;
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def VLSEG#nf#E256FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth256, "vlseg"#nf#"e256ff.v">;
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def VLSEG#nf#E512FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth512, "vlseg"#nf#"e512ff.v">;
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def VLSEG#nf#E1024FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth1024, "vlseg"#nf#"e1024ff.v">;
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def VSSEG#nf#E8_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth8, "vsseg"#nf#"e8.v">;
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def VSSEG#nf#E16_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth16, "vsseg"#nf#"e16.v">;
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def VSSEG#nf#E32_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth32, "vsseg"#nf#"e32.v">;
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def VSSEG#nf#E64_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">;
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def VSSEG#nf#E128_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth128, "vsseg"#nf#"e128.v">;
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def VSSEG#nf#E256_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth256, "vsseg"#nf#"e256.v">;
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def VSSEG#nf#E512_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth512, "vsseg"#nf#"e512.v">;
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def VSSEG#nf#E1024_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth1024, "vsseg"#nf#"e1024.v">;
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// Vector Strided Instructions
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def VLSSEG#nf#E8_V : VStridedSegmentLoad<!add(nf, -1), LSWidth8, "vlsseg"#nf#"e8.v">;
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def VLSSEG#nf#E16_V : VStridedSegmentLoad<!add(nf, -1), LSWidth16, "vlsseg"#nf#"e16.v">;
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def VLSSEG#nf#E32_V : VStridedSegmentLoad<!add(nf, -1), LSWidth32, "vlsseg"#nf#"e32.v">;
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def VLSSEG#nf#E64_V : VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">;
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def VLSSEG#nf#E128_V : VStridedSegmentLoad<!add(nf, -1), LSWidth128, "vlsseg"#nf#"e128.v">;
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def VLSSEG#nf#E256_V : VStridedSegmentLoad<!add(nf, -1), LSWidth256, "vlsseg"#nf#"e256.v">;
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def VLSSEG#nf#E512_V : VStridedSegmentLoad<!add(nf, -1), LSWidth512, "vlsseg"#nf#"e512.v">;
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def VLSSEG#nf#E1024_V : VStridedSegmentLoad<!add(nf, -1), LSWidth1024, "vlsseg"#nf#"e1024.v">;
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def VSSSEG#nf#E8_V : VStridedSegmentStore<!add(nf, -1), LSWidth8, "vssseg"#nf#"e8.v">;
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def VSSSEG#nf#E16_V : VStridedSegmentStore<!add(nf, -1), LSWidth16, "vssseg"#nf#"e16.v">;
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def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">;
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def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
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def VSSSEG#nf#E128_V : VStridedSegmentStore<!add(nf, -1), LSWidth128, "vssseg"#nf#"e128.v">;
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def VSSSEG#nf#E256_V : VStridedSegmentStore<!add(nf, -1), LSWidth256, "vssseg"#nf#"e256.v">;
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def VSSSEG#nf#E512_V : VStridedSegmentStore<!add(nf, -1), LSWidth512, "vssseg"#nf#"e512.v">;
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def VSSSEG#nf#E1024_V : VStridedSegmentStore<!add(nf, -1), LSWidth1024, "vssseg"#nf#"e1024.v">;
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// Vector Indexed Instructions
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def VLXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth8, "vlxseg"#nf#"ei8.v">;
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def VLXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth16, "vlxseg"#nf#"ei16.v">;
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def VLXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth32, "vlxseg"#nf#"ei32.v">;
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def VLXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth64, "vlxseg"#nf#"ei64.v">;
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def VLXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth128, "vlxseg"#nf#"ei128.v">;
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def VLXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth256, "vlxseg"#nf#"ei256.v">;
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def VLXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth512, "vlxseg"#nf#"ei512.v">;
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def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth1024, "vlxseg"#nf#"ei1024.v">;
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def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), LSWidth8, "vsxseg"#nf#"ei8.v">;
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def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), LSWidth16, "vsxseg"#nf#"ei16.v">;
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def VSXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), LSWidth32, "vsxseg"#nf#"ei32.v">;
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def VSXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), LSWidth64, "vsxseg"#nf#"ei64.v">;
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def VSXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), LSWidth128, "vsxseg"#nf#"ei128.v">;
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def VSXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), LSWidth256, "vsxseg"#nf#"ei256.v">;
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def VSXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), LSWidth512, "vsxseg"#nf#"ei512.v">;
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def VSXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), LSWidth1024, "vsxseg"#nf#"ei1024.v">;
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}
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} // Predicates = [HasStdExtZvlsseg]

‎llvm/lib/Target/RISCV/RISCVSchedRocket32.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ def Rocket32Model : SchedMachineModel {
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = 1;
20-
let UnsupportedFeatures = [HasStdExtV];
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let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
2121
}
2222

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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSchedRocket64.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def Rocket64Model : SchedMachineModel {
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let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
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let LoadLatency = 3;
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let MispredictPenalty = 3;
19-
let UnsupportedFeatures = [HasStdExtV];
19+
let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
2020
}
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

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@@ -51,6 +51,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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bool HasStdExtZbt = false;
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bool HasStdExtZbproposedc = false;
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bool HasStdExtV = false;
54+
bool HasStdExtZvlsseg = false;
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bool HasRV64 = false;
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bool IsRV32E = false;
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bool EnableLinkerRelax = false;
@@ -112,6 +113,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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bool hasStdExtZbt() const { return HasStdExtZbt; }
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bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
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bool hasStdExtV() const { return HasStdExtV; }
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bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
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bool is64Bit() const { return HasRV64; }
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bool isRV32E() const { return IsRV32E; }
117119
bool enableLinkerRelax() const { return EnableLinkerRelax; }

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