[AMDGPU] Kill temporary register after restoring

Not a correctness issue, but the temporary register is not used
afterwards and should be dead.

Differential Revision: https://reviews.llvm.org/D100295

Author: Flakebi

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -228,15 +228,15 @@ struct SGPRSpillBuilder {
       // Add an implicit use of the load so it is not dead.
       // FIXME This inserts an unnecessary waitcnt
       if (!TmpVGPRLive) {
-        I.addReg(TmpVGPR, RegState::Implicit);
+        I.addReg(TmpVGPR, RegState::ImplicitKill);
       }
     } else {
       // Restore inactive lanes
       TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
                                   /*IsKill*/ false);
       auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
       if (!TmpVGPRLive) {
-        I.addReg(TmpVGPR, RegState::Implicit);
+        I.addReg(TmpVGPR, RegState::ImplicitKill);
       }
       // Restore active lanes
       if (TmpVGPRLive)

llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll

@@ -60,12 +60,12 @@ define void @callee_with_stack_and_call() #0 {
 ; NO-SPILL-TO-VGPR-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; NO-SPILL-TO-VGPR-NEXT:    s_mov_b64 s[6:7], exec
 ; NO-SPILL-TO-VGPR-NEXT:    s_mov_b64 exec, 3
-; NO-SPILL-TO-VGPR-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:16
-; NO-SPILL-TO-VGPR-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; NO-SPILL-TO-VGPR-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:16
+; NO-SPILL-TO-VGPR-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
 ; NO-SPILL-TO-VGPR-NEXT:    s_waitcnt vmcnt(0)
-; NO-SPILL-TO-VGPR-NEXT:    v_readlane_b32 s4, v2, 0
-; NO-SPILL-TO-VGPR-NEXT:    v_readlane_b32 s5, v2, 1
-; NO-SPILL-TO-VGPR-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:16
+; NO-SPILL-TO-VGPR-NEXT:    v_readlane_b32 s4, v1, 0
+; NO-SPILL-TO-VGPR-NEXT:    v_readlane_b32 s5, v1, 1
+; NO-SPILL-TO-VGPR-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:16
 ; NO-SPILL-TO-VGPR-NEXT:    s_waitcnt vmcnt(0)
 ; NO-SPILL-TO-VGPR-NEXT:    s_mov_b64 exec, s[6:7]
 ; NO-SPILL-TO-VGPR-NEXT:    s_sub_u32 s32, s32, 0x800