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Merge commit '21fe8b635cfb' from llvm.org/main into next
2 parents 3f0104b + 21fe8b6 commit 704ba9a

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mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,7 @@ bool vector::isContiguousSlice(MemRefType memrefType, VectorType vectorType) {
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return false;
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// Cond 1: A contiguous memref will always have a unit trailing stride.
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if (strides.back() != 1)
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if (strides.empty() || strides.back() != 1)
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return false;
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// Cond 2: Strides of a contiguous memref have to match the flattened dims.

mlir/test/Dialect/Vector/vector-transfer-flatten.mlir

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -356,3 +356,18 @@ func.func @fold_unit_dims_entirely(%arg0 : vector<8xi32>,
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// CHECK: %[[VAL_3:.*]] = arith.muli %[[VAL_0]], %[[VAL_1]] : vector<8xi32>
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// CHECK: %[[VAL_4:.*]] = arith.addi %[[VAL_3]], %[[VAL_2]] : vector<8xi32>
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// CHECK: return %[[VAL_4]] : vector<8xi32>
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// -----
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// This test is to make sure there is no crash for empty stride.
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func.func @stride_empty_test(%1: memref<i16>) -> vector<32x256xi16> {
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%c0_i16 = arith.constant 0 : i16
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%3 = vector.transfer_read %1[], %c0_i16 {permutation_map = affine_map<() -> (0, 0)>} : memref<i16>, vector<32x256xi16>
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return %3 : vector<32x256xi16>
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// CHECK-LABEL: func.func @stride_empty_test
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// CHECK: %[[VAL:.*]] = arith.constant 0 : i16
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// CHECK: %[[RET:.*]] = vector.transfer_read {{.*}} vector<32x256xi16>
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// CHECK: return %[[RET]]
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// CHECK-NOT: empty()
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}

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