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[RISCV] Split and rename WriteVISlideX into WriteVSlideUpX and WriteVSlideDownX (llvm#92605)
Some processors might have different latencies and/or rthroughput for slide up and down operations on integer vectors, yet there is only a single SchedWrite for both of them at this moment. This patch splits this SchedWrite into two as well as drop the "I" before "Slide" since such information is redundant. We also do the same renaming on `WriteVISlideI`. Note that we only split the X variant (i.e. using a register value for index offset) for now. This is effectively NFC.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -975,11 +975,14 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
975975
SchedUnaryMC<"WriteVNClipI", "ReadVNClipV">;
976976
}
977977

978-
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6> {
978+
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> {
979+
// Note: In the future, if VISlideI is also split into VSlideUpI and
980+
// VSlideDownI, it'll probably better to use two separate multiclasses.
981+
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
979982
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
980-
SchedBinaryMC<"WriteVISlideX", "ReadVISlideV", "ReadVISlideX">;
983+
SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
981984
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
982-
SchedUnaryMC<"WriteVISlideI", "ReadVISlideV">;
985+
SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">;
983986
}
984987

985988
multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
@@ -1658,10 +1661,10 @@ def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
16581661
let Predicates = [HasVInstructions] in {
16591662
// Vector Slide Instructions
16601663
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
1661-
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110>;
1664+
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
16621665
defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
16631666
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
1664-
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111>;
1667+
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
16651668
defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
16661669
} // Predicates = [HasVInstructions]
16671670

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3380,14 +3380,16 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
33803380
}
33813381
}
33823382

3383-
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
3383+
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, bit slidesUp = false,
3384+
string Constraint = ""> {
3385+
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
33843386
foreach m = MxList in {
33853387
defvar mx = m.MX;
33863388
defm "" : VPseudoVSLDV_VX<m, Constraint>,
3387-
SchedTernary<"WriteVISlideX", "ReadVISlideV", "ReadVISlideV",
3389+
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
33883390
"ReadVISlideX", mx>;
33893391
defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
3390-
SchedBinary<"WriteVISlideI", "ReadVISlideV", "ReadVISlideV", mx>;
3392+
SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
33913393
}
33923394
}
33933395

@@ -6861,8 +6863,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
68616863
// 16.3. Vector Slide Instructions
68626864
//===----------------------------------------------------------------------===//
68636865
let Predicates = [HasVInstructions] in {
6864-
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI<uimm5, "@earlyclobber $rd">;
6865-
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI<uimm5>;
6866+
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/true, "@earlyclobber $rd">;
6867+
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/false>;
68666868
defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
68676869
defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
68686870
} // Predicates = [HasVInstructions]

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -937,10 +937,11 @@ foreach mx = SchedMxList in {
937937
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
938938
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
939939
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
940-
defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
941-
defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
942-
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
943-
defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
940+
defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
941+
defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
942+
defm "" : LMULWriteResMX<"WriteVSlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
943+
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
944+
defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
944945
}
945946
}
946947

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -669,7 +669,7 @@ foreach mx = SchedMxList in {
669669
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
670670
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
671671
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
672-
defm "" : LMULWriteResMX<"WriteVISlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
672+
defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
673673
}
674674
let Latency = 1, ReleaseAtCycles = [LMulLat] in {
675675
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
@@ -679,7 +679,8 @@ foreach mx = SchedMxList in {
679679
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
680680
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
681681
let Latency = 2, ReleaseAtCycles = [1] in {
682-
defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
682+
defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
683+
defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
683684
}
684685
}
685686

@@ -688,7 +689,8 @@ foreach mx = ["M8", "M4", "M2"] in {
688689
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
689690
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
690691
let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {
691-
defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
692+
defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
693+
defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
692694
}
693695
}
694696

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -514,8 +514,9 @@ def WriteVMovXS : SchedWrite;
514514
def WriteVMovSF : SchedWrite;
515515
def WriteVMovFS : SchedWrite;
516516
// 16.3. Vector Slide Instructions
517-
defm "" : LMULSchedWrites<"WriteVISlideX">;
518-
defm "" : LMULSchedWrites<"WriteVISlideI">;
517+
defm "" : LMULSchedWrites<"WriteVSlideUpX">;
518+
defm "" : LMULSchedWrites<"WriteVSlideDownX">;
519+
defm "" : LMULSchedWrites<"WriteVSlideI">;
519520
defm "" : LMULSchedWrites<"WriteVISlide1X">;
520521
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
521522
// 16.4. Vector Register Gather Instructions
@@ -949,8 +950,9 @@ def : WriteRes<WriteVMovSX, []>;
949950
def : WriteRes<WriteVMovXS, []>;
950951
def : WriteRes<WriteVMovSF, []>;
951952
def : WriteRes<WriteVMovFS, []>;
952-
defm "" : LMULWriteRes<"WriteVISlideX", []>;
953-
defm "" : LMULWriteRes<"WriteVISlideI", []>;
953+
defm "" : LMULWriteRes<"WriteVSlideUpX", []>;
954+
defm "" : LMULWriteRes<"WriteVSlideDownX", []>;
955+
defm "" : LMULWriteRes<"WriteVSlideI", []>;
954956
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
955957
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
956958
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;

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