Skip to content

Commit 722d792

Browse files
rampitecrampitec
committed
[AMDGPU] Reorganize VOP3P encoding
This changes width of encoding and opcode fields to match the documentation. Differential Revision: https://reviews.llvm.org/D88619
1 parent 7475bd5 commit 722d792

File tree

2 files changed

+95
-95
lines changed

2 files changed

+95
-95
lines changed

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 87 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -418,103 +418,103 @@ def V_MFMA_F32_32X32X4BF16 : VOP3Inst<"v_mfma_f32_32x32x4bf16", VOPProfileMAI_F3
418418
def : MnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">;
419419
def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
420420

421-
multiclass VOP3P_Real_vi<bits<10> op> {
421+
multiclass VOP3P_Real_vi<bits<7> op> {
422422
def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
423423
VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
424424
let AssemblerPredicate = HasVOP3PInsts;
425425
let DecoderNamespace = "GFX8";
426426
}
427427
}
428428

429-
multiclass VOP3P_Real_MAI<bits<10> op> {
429+
multiclass VOP3P_Real_MAI<bits<7> op> {
430430
def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
431431
VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
432432
let AssemblerPredicate = HasMAIInsts;
433433
let DecoderNamespace = "GFX8";
434434
}
435435
}
436436

437-
defm V_PK_MAD_I16 : VOP3P_Real_vi <0x380>;
438-
defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x381>;
439-
defm V_PK_ADD_I16 : VOP3P_Real_vi <0x382>;
440-
defm V_PK_SUB_I16 : VOP3P_Real_vi <0x383>;
441-
defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x384>;
442-
defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x385>;
443-
defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x386>;
444-
defm V_PK_MAX_I16 : VOP3P_Real_vi <0x387>;
445-
defm V_PK_MIN_I16 : VOP3P_Real_vi <0x388>;
446-
defm V_PK_MAD_U16 : VOP3P_Real_vi <0x389>;
447-
448-
defm V_PK_ADD_U16 : VOP3P_Real_vi <0x38a>;
449-
defm V_PK_SUB_U16 : VOP3P_Real_vi <0x38b>;
450-
defm V_PK_MAX_U16 : VOP3P_Real_vi <0x38c>;
451-
defm V_PK_MIN_U16 : VOP3P_Real_vi <0x38d>;
452-
defm V_PK_FMA_F16 : VOP3P_Real_vi <0x38e>;
453-
defm V_PK_ADD_F16 : VOP3P_Real_vi <0x38f>;
454-
defm V_PK_MUL_F16 : VOP3P_Real_vi <0x390>;
455-
defm V_PK_MIN_F16 : VOP3P_Real_vi <0x391>;
456-
defm V_PK_MAX_F16 : VOP3P_Real_vi <0x392>;
437+
defm V_PK_MAD_I16 : VOP3P_Real_vi <0x00>;
438+
defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x01>;
439+
defm V_PK_ADD_I16 : VOP3P_Real_vi <0x02>;
440+
defm V_PK_SUB_I16 : VOP3P_Real_vi <0x03>;
441+
defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x04>;
442+
defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x05>;
443+
defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x06>;
444+
defm V_PK_MAX_I16 : VOP3P_Real_vi <0x07>;
445+
defm V_PK_MIN_I16 : VOP3P_Real_vi <0x08>;
446+
defm V_PK_MAD_U16 : VOP3P_Real_vi <0x09>;
447+
448+
defm V_PK_ADD_U16 : VOP3P_Real_vi <0x0a>;
449+
defm V_PK_SUB_U16 : VOP3P_Real_vi <0x0b>;
450+
defm V_PK_MAX_U16 : VOP3P_Real_vi <0x0c>;
451+
defm V_PK_MIN_U16 : VOP3P_Real_vi <0x0d>;
452+
defm V_PK_FMA_F16 : VOP3P_Real_vi <0x0e>;
453+
defm V_PK_ADD_F16 : VOP3P_Real_vi <0x0f>;
454+
defm V_PK_MUL_F16 : VOP3P_Real_vi <0x10>;
455+
defm V_PK_MIN_F16 : VOP3P_Real_vi <0x11>;
456+
defm V_PK_MAX_F16 : VOP3P_Real_vi <0x12>;
457457

458458

459459
let SubtargetPredicate = HasMadMixInsts in {
460-
defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x3a0>;
461-
defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x3a1>;
462-
defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x3a2>;
460+
defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x20>;
461+
defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x21>;
462+
defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x22>;
463463
}
464464

465465
let SubtargetPredicate = HasFmaMixInsts in {
466466
let DecoderNamespace = "GFX9_DL" in {
467467
// The mad_mix instructions were renamed and their behaviors changed,
468468
// but the opcode stayed the same so we need to put these in a
469469
// different DecoderNamespace to avoid the ambiguity.
470-
defm V_FMA_MIX_F32 : VOP3P_Real_vi <0x3a0>;
471-
defm V_FMA_MIXLO_F16 : VOP3P_Real_vi <0x3a1>;
472-
defm V_FMA_MIXHI_F16 : VOP3P_Real_vi <0x3a2>;
470+
defm V_FMA_MIX_F32 : VOP3P_Real_vi <0x20>;
471+
defm V_FMA_MIXLO_F16 : VOP3P_Real_vi <0x21>;
472+
defm V_FMA_MIXHI_F16 : VOP3P_Real_vi <0x22>;
473473
}
474474
}
475475

476476

477477
let SubtargetPredicate = HasDot2Insts in {
478478

479-
defm V_DOT2_F32_F16 : VOP3P_Real_vi <0x3a3>;
480-
defm V_DOT2_I32_I16 : VOP3P_Real_vi <0x3a6>;
481-
defm V_DOT2_U32_U16 : VOP3P_Real_vi <0x3a7>;
482-
defm V_DOT4_U32_U8 : VOP3P_Real_vi <0x3a9>;
483-
defm V_DOT8_U32_U4 : VOP3P_Real_vi <0x3ab>;
479+
defm V_DOT2_F32_F16 : VOP3P_Real_vi <0x23>;
480+
defm V_DOT2_I32_I16 : VOP3P_Real_vi <0x26>;
481+
defm V_DOT2_U32_U16 : VOP3P_Real_vi <0x27>;
482+
defm V_DOT4_U32_U8 : VOP3P_Real_vi <0x29>;
483+
defm V_DOT8_U32_U4 : VOP3P_Real_vi <0x2b>;
484484

485485
} // End SubtargetPredicate = HasDot2Insts
486486

487487
let SubtargetPredicate = HasDot1Insts in {
488488

489-
defm V_DOT4_I32_I8 : VOP3P_Real_vi <0x3a8>;
490-
defm V_DOT8_I32_I4 : VOP3P_Real_vi <0x3aa>;
489+
defm V_DOT4_I32_I8 : VOP3P_Real_vi <0x28>;
490+
defm V_DOT8_I32_I4 : VOP3P_Real_vi <0x2a>;
491491

492492
} // End SubtargetPredicate = HasDot1Insts
493493

494494
let SubtargetPredicate = HasMAIInsts in {
495495

496-
defm V_ACCVGPR_READ_B32 : VOP3P_Real_MAI <0x3d8>;
497-
defm V_ACCVGPR_WRITE_B32 : VOP3P_Real_MAI <0x3d9>;
498-
defm V_MFMA_F32_32X32X1F32 : VOP3P_Real_MAI <0x3c0>;
499-
defm V_MFMA_F32_16X16X1F32 : VOP3P_Real_MAI <0x3c1>;
500-
defm V_MFMA_F32_4X4X1F32 : VOP3P_Real_MAI <0x3c2>;
501-
defm V_MFMA_F32_32X32X2F32 : VOP3P_Real_MAI <0x3c4>;
502-
defm V_MFMA_F32_16X16X4F32 : VOP3P_Real_MAI <0x3c5>;
503-
defm V_MFMA_F32_32X32X4F16 : VOP3P_Real_MAI <0x3c8>;
504-
defm V_MFMA_F32_16X16X4F16 : VOP3P_Real_MAI <0x3c9>;
505-
defm V_MFMA_F32_4X4X4F16 : VOP3P_Real_MAI <0x3ca>;
506-
defm V_MFMA_F32_32X32X8F16 : VOP3P_Real_MAI <0x3cc>;
507-
defm V_MFMA_F32_16X16X16F16 : VOP3P_Real_MAI <0x3cd>;
508-
defm V_MFMA_I32_32X32X4I8 : VOP3P_Real_MAI <0x3d0>;
509-
defm V_MFMA_I32_16X16X4I8 : VOP3P_Real_MAI <0x3d1>;
510-
defm V_MFMA_I32_4X4X4I8 : VOP3P_Real_MAI <0x3d2>;
511-
defm V_MFMA_I32_32X32X8I8 : VOP3P_Real_MAI <0x3d4>;
512-
defm V_MFMA_I32_16X16X16I8 : VOP3P_Real_MAI <0x3d5>;
513-
defm V_MFMA_F32_32X32X2BF16 : VOP3P_Real_MAI <0x3e8>;
514-
defm V_MFMA_F32_16X16X2BF16 : VOP3P_Real_MAI <0x3e9>;
515-
defm V_MFMA_F32_4X4X2BF16 : VOP3P_Real_MAI <0x3eb>;
516-
defm V_MFMA_F32_32X32X4BF16 : VOP3P_Real_MAI <0x3ec>;
517-
defm V_MFMA_F32_16X16X8BF16 : VOP3P_Real_MAI <0x3ed>;
496+
defm V_ACCVGPR_READ_B32 : VOP3P_Real_MAI <0x58>;
497+
defm V_ACCVGPR_WRITE_B32 : VOP3P_Real_MAI <0x59>;
498+
defm V_MFMA_F32_32X32X1F32 : VOP3P_Real_MAI <0x40>;
499+
defm V_MFMA_F32_16X16X1F32 : VOP3P_Real_MAI <0x41>;
500+
defm V_MFMA_F32_4X4X1F32 : VOP3P_Real_MAI <0x42>;
501+
defm V_MFMA_F32_32X32X2F32 : VOP3P_Real_MAI <0x44>;
502+
defm V_MFMA_F32_16X16X4F32 : VOP3P_Real_MAI <0x45>;
503+
defm V_MFMA_F32_32X32X4F16 : VOP3P_Real_MAI <0x48>;
504+
defm V_MFMA_F32_16X16X4F16 : VOP3P_Real_MAI <0x49>;
505+
defm V_MFMA_F32_4X4X4F16 : VOP3P_Real_MAI <0x4a>;
506+
defm V_MFMA_F32_32X32X8F16 : VOP3P_Real_MAI <0x4c>;
507+
defm V_MFMA_F32_16X16X16F16 : VOP3P_Real_MAI <0x4d>;
508+
defm V_MFMA_I32_32X32X4I8 : VOP3P_Real_MAI <0x50>;
509+
defm V_MFMA_I32_16X16X4I8 : VOP3P_Real_MAI <0x51>;
510+
defm V_MFMA_I32_4X4X4I8 : VOP3P_Real_MAI <0x52>;
511+
defm V_MFMA_I32_32X32X8I8 : VOP3P_Real_MAI <0x54>;
512+
defm V_MFMA_I32_16X16X16I8 : VOP3P_Real_MAI <0x55>;
513+
defm V_MFMA_F32_32X32X2BF16 : VOP3P_Real_MAI <0x68>;
514+
defm V_MFMA_F32_16X16X2BF16 : VOP3P_Real_MAI <0x69>;
515+
defm V_MFMA_F32_4X4X2BF16 : VOP3P_Real_MAI <0x6b>;
516+
defm V_MFMA_F32_32X32X4BF16 : VOP3P_Real_MAI <0x6c>;
517+
defm V_MFMA_F32_16X16X8BF16 : VOP3P_Real_MAI <0x6d>;
518518

519519
} // End SubtargetPredicate = HasMAIInsts
520520

@@ -523,48 +523,48 @@ defm V_MFMA_F32_16X16X8BF16 : VOP3P_Real_MAI <0x3ed>;
523523
//===----------------------------------------------------------------------===//
524524

525525
let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
526-
multiclass VOP3P_Real_gfx10<bits<10> op> {
526+
multiclass VOP3P_Real_gfx10<bits<7> op> {
527527
def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
528528
VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>;
529529
}
530530
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
531531

532-
defm V_PK_MAD_I16 : VOP3P_Real_gfx10<0x000>;
533-
defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10<0x001>;
534-
defm V_PK_ADD_I16 : VOP3P_Real_gfx10<0x002>;
535-
defm V_PK_SUB_I16 : VOP3P_Real_gfx10<0x003>;
536-
defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10<0x004>;
537-
defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10<0x005>;
538-
defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10<0x006>;
539-
defm V_PK_MAX_I16 : VOP3P_Real_gfx10<0x007>;
540-
defm V_PK_MIN_I16 : VOP3P_Real_gfx10<0x008>;
541-
defm V_PK_MAD_U16 : VOP3P_Real_gfx10<0x009>;
542-
defm V_PK_ADD_U16 : VOP3P_Real_gfx10<0x00a>;
543-
defm V_PK_SUB_U16 : VOP3P_Real_gfx10<0x00b>;
544-
defm V_PK_MAX_U16 : VOP3P_Real_gfx10<0x00c>;
545-
defm V_PK_MIN_U16 : VOP3P_Real_gfx10<0x00d>;
546-
defm V_PK_FMA_F16 : VOP3P_Real_gfx10<0x00e>;
547-
defm V_PK_ADD_F16 : VOP3P_Real_gfx10<0x00f>;
548-
defm V_PK_MUL_F16 : VOP3P_Real_gfx10<0x010>;
549-
defm V_PK_MIN_F16 : VOP3P_Real_gfx10<0x011>;
550-
defm V_PK_MAX_F16 : VOP3P_Real_gfx10<0x012>;
551-
defm V_FMA_MIX_F32 : VOP3P_Real_gfx10<0x020>;
552-
defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10<0x021>;
553-
defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10<0x022>;
532+
defm V_PK_MAD_I16 : VOP3P_Real_gfx10<0x00>;
533+
defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10<0x01>;
534+
defm V_PK_ADD_I16 : VOP3P_Real_gfx10<0x02>;
535+
defm V_PK_SUB_I16 : VOP3P_Real_gfx10<0x03>;
536+
defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10<0x04>;
537+
defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10<0x05>;
538+
defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10<0x06>;
539+
defm V_PK_MAX_I16 : VOP3P_Real_gfx10<0x07>;
540+
defm V_PK_MIN_I16 : VOP3P_Real_gfx10<0x08>;
541+
defm V_PK_MAD_U16 : VOP3P_Real_gfx10<0x09>;
542+
defm V_PK_ADD_U16 : VOP3P_Real_gfx10<0x0a>;
543+
defm V_PK_SUB_U16 : VOP3P_Real_gfx10<0x0b>;
544+
defm V_PK_MAX_U16 : VOP3P_Real_gfx10<0x0c>;
545+
defm V_PK_MIN_U16 : VOP3P_Real_gfx10<0x0d>;
546+
defm V_PK_FMA_F16 : VOP3P_Real_gfx10<0x0e>;
547+
defm V_PK_ADD_F16 : VOP3P_Real_gfx10<0x0f>;
548+
defm V_PK_MUL_F16 : VOP3P_Real_gfx10<0x10>;
549+
defm V_PK_MIN_F16 : VOP3P_Real_gfx10<0x11>;
550+
defm V_PK_MAX_F16 : VOP3P_Real_gfx10<0x12>;
551+
defm V_FMA_MIX_F32 : VOP3P_Real_gfx10<0x20>;
552+
defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10<0x21>;
553+
defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10<0x22>;
554554

555555
let SubtargetPredicate = HasDot2Insts in {
556556

557-
defm V_DOT2_F32_F16 : VOP3P_Real_gfx10 <0x013>;
558-
defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x014>;
559-
defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x015>;
560-
defm V_DOT4_U32_U8 : VOP3P_Real_gfx10 <0x017>;
561-
defm V_DOT8_U32_U4 : VOP3P_Real_gfx10 <0x019>;
557+
defm V_DOT2_F32_F16 : VOP3P_Real_gfx10 <0x13>;
558+
defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x14>;
559+
defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x15>;
560+
defm V_DOT4_U32_U8 : VOP3P_Real_gfx10 <0x17>;
561+
defm V_DOT8_U32_U4 : VOP3P_Real_gfx10 <0x19>;
562562

563563
} // End SubtargetPredicate = HasDot2Insts
564564

565565
let SubtargetPredicate = HasDot1Insts in {
566566

567-
defm V_DOT4_I32_I8 : VOP3P_Real_gfx10 <0x016>;
568-
defm V_DOT8_I32_I4 : VOP3P_Real_gfx10 <0x018>;
567+
defm V_DOT4_I32_I8 : VOP3P_Real_gfx10 <0x16>;
568+
defm V_DOT8_I32_I4 : VOP3P_Real_gfx10 <0x18>;
569569

570570
} // End SubtargetPredicate = HasDot1Insts

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,7 @@ class VOP3be <VOPProfile P> : Enc64 {
296296
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
297297
}
298298

299-
class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
299+
class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 {
300300
bits<8> vdst;
301301
// neg, neg_hi, op_sel put in srcN_modifiers
302302
bits<4> src0_modifiers;
@@ -320,8 +320,8 @@ class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
320320

321321
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
322322

323-
let Inst{25-16} = op;
324-
let Inst{31-26} = 0x34; //encoding
323+
let Inst{22-16} = op;
324+
let Inst{31-23} = 0x1a7; //encoding
325325
let Inst{40-32} = !if(P.HasSrc0, src0, 0);
326326
let Inst{49-41} = !if(P.HasSrc1, src1, 0);
327327
let Inst{58-50} = !if(P.HasSrc2, src2, 0);
@@ -332,7 +332,7 @@ class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
332332
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo)
333333
}
334334

335-
class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 {
335+
class VOP3Pe_MAI <bits<7> op, VOPProfile P> : Enc64 {
336336
bits<8> vdst;
337337
bits<10> src0;
338338
bits<10> src1;
@@ -349,8 +349,8 @@ class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 {
349349

350350
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
351351

352-
let Inst{25-16} = op;
353-
let Inst{31-26} = 0x34; //encoding
352+
let Inst{22-16} = op;
353+
let Inst{31-23} = 0x1a7; //encoding
354354
let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
355355
let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
356356
let Inst{58-50} = !if(P.HasSrc2, src2, 0);
@@ -362,8 +362,8 @@ class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 {
362362
}
363363

364364

365-
class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> {
366-
let Inst{31-26} = 0x33; //encoding
365+
class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> {
366+
let Inst{31-23} = 0x198; //encoding
367367
}
368368

369369
class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {

0 commit comments

Comments
 (0)