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AMDGPU/GlobalISel: Rewrite fadd select tests
Convert to the style most others use with one test instruction per function, and use an implicit use to ensure the result register class is constrained. Change-Id: I6109148b0e3c80aa5535796a37abca583c19a936
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir

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‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
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---
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name: fadd_s16_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vsv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_vsv
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; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vvs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_vvs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vvv_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %2
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%5:vgpr(s16) = G_FADD %4, %3
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S_ENDPGM 0, implicit %5
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...
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---
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name: fadd_s16_vvv_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %3
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%5:vgpr(s16) = G_FADD %2, %4
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S_ENDPGM 0, implicit %5
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...
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---
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name: fadd_s16_vvv_fneg_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %2
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%5:vgpr(s16) = G_FNEG %4
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%6:vgpr(s16) = G_FADD %5, %3
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s16_vvv_fneg_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %3
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%5:vgpr(s16) = G_FNEG %4
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%6:vgpr(s16) = G_FADD %2, %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s16_fneg_copy_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:sgpr(s16) = G_FNEG %3
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%5:vgpr(s16) = G_FADD %2, %4
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S_ENDPGM 0, implicit %5
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...

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