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[RISCV] Add Zvfhmin extension support for llvm RISCV backend
This patch supports Zvfhmin for RISCV codegen. Reviewed By: michaelmaitland Differential Revision: https://reviews.llvm.org/D151414
1 parent 4d4ed5b commit 7599035

16 files changed

+128
-25
lines changed

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
143143
{"zve64x", RISCVExtensionVersion{1, 0}},
144144

145145
{"zvfh", RISCVExtensionVersion{1, 0}},
146+
{"zvfhmin", RISCVExtensionVersion{1, 0}},
146147

147148
{"zvl1024b", RISCVExtensionVersion{1, 0}},
148149
{"zvl128b", RISCVExtensionVersion{1, 0}},
@@ -985,6 +986,7 @@ static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
985986
static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
986987
static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
987988
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
989+
static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
988990
static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
989991
static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
990992
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -1051,6 +1053,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
10511053
{{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
10521054
{{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
10531055
{{"zvfh"}, {ImpliedExtsZvfh}},
1056+
{{"zvfhmin"}, {ImpliedExtsZvfhmin}},
10541057
{{"zvkn"}, {ImpliedExtsZvkn}},
10551058
{{"zvknc"}, {ImpliedExtsZvknc}},
10561059
{{"zvkng"}, {ImpliedExtsZvkng}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -492,8 +492,18 @@ def FeatureStdExtZvfh
492492
"'Zvfh' (Vector Half-Precision Floating-Point)",
493493
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
494494

495+
def FeatureStdExtZvfhmin
496+
: SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
497+
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
498+
[FeatureStdExtZve32f]>;
499+
495500
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
496501

502+
def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
503+
AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
504+
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
505+
"'Zvfh' (Vector Half-Precision Floating-Point)">;
506+
497507
def HasStdExtZfhOrZvfh
498508
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
499509
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 48 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
186186
addRegClassForRVV(VT);
187187
}
188188

189-
if (Subtarget.hasVInstructionsF16())
189+
if (Subtarget.hasVInstructionsF16Minimal())
190190
for (MVT VT : F16VecVTs)
191191
addRegClassForRVV(VT);
192192

@@ -910,6 +910,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
910910
continue;
911911
SetCommonVFPActions(VT);
912912
}
913+
} else if (Subtarget.hasVInstructionsF16Minimal()) {
914+
for (MVT VT : F16VecVTs) {
915+
if (!isTypeLegal(VT))
916+
continue;
917+
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
918+
setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
919+
// TODO: make others promote?
920+
}
913921
}
914922

915923
if (Subtarget.hasVInstructionsF32()) {
@@ -1093,6 +1101,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
10931101
// expansion to a build_vector of 0s.
10941102
setOperationAction(ISD::UNDEF, VT, Custom);
10951103

1104+
if (VT.getVectorElementType() == MVT::f16 &&
1105+
!Subtarget.hasVInstructionsF16()) {
1106+
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
1107+
setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
1108+
// TODO: make others promote?
1109+
continue;
1110+
}
1111+
10961112
// We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
10971113
setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT,
10981114
Custom);
@@ -2260,7 +2276,7 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
22602276
return false;
22612277
break;
22622278
case MVT::f16:
2263-
if (!Subtarget.hasVInstructionsF16())
2279+
if (!Subtarget.hasVInstructionsF16Minimal())
22642280
return false;
22652281
break;
22662282
case MVT::f32:
@@ -12338,10 +12354,18 @@ static SDValue combineVFMADD_VLWithVFNEG_VL(SDNode *N, SelectionDAG &DAG) {
1233812354
VL);
1233912355
}
1234012356

12341-
static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
12357+
static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG,
12358+
const RISCVSubtarget &Subtarget) {
1234212359
if (SDValue V = combineVFMADD_VLWithVFNEG_VL(N, DAG))
1234312360
return V;
1234412361

12362+
if (N->getValueType(0).isScalableVector() &&
12363+
N->getValueType(0).getVectorElementType() == MVT::f32 &&
12364+
(Subtarget.hasVInstructionsF16Minimal() &&
12365+
!Subtarget.hasVInstructionsF16())) {
12366+
return SDValue();
12367+
}
12368+
1234512369
// FIXME: Ignore strict opcodes for now.
1234612370
if (N->isTargetStrictFPOpcode())
1234712371
return SDValue();
@@ -12392,7 +12416,15 @@ static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
1239212416
N->getOperand(2), Mask, VL);
1239312417
}
1239412418

12395-
static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG) {
12419+
static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG,
12420+
const RISCVSubtarget &Subtarget) {
12421+
if (N->getValueType(0).isScalableVector() &&
12422+
N->getValueType(0).getVectorElementType() == MVT::f32 &&
12423+
(Subtarget.hasVInstructionsF16Minimal() &&
12424+
!Subtarget.hasVInstructionsF16())) {
12425+
return SDValue();
12426+
}
12427+
1239612428
// FIXME: Ignore strict opcodes for now.
1239712429
assert(!N->isTargetStrictFPOpcode() && "Unexpected opcode");
1239812430

@@ -12425,7 +12457,15 @@ static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG) {
1242512457
Op1, Merge, Mask, VL);
1242612458
}
1242712459

12428-
static SDValue performFADDSUB_VLCombine(SDNode *N, SelectionDAG &DAG) {
12460+
static SDValue performFADDSUB_VLCombine(SDNode *N, SelectionDAG &DAG,
12461+
const RISCVSubtarget &Subtarget) {
12462+
if (N->getValueType(0).isScalableVector() &&
12463+
N->getValueType(0).getVectorElementType() == MVT::f32 &&
12464+
(Subtarget.hasVInstructionsF16Minimal() &&
12465+
!Subtarget.hasVInstructionsF16())) {
12466+
return SDValue();
12467+
}
12468+
1242912469
SDValue Op0 = N->getOperand(0);
1243012470
SDValue Op1 = N->getOperand(1);
1243112471
SDValue Merge = N->getOperand(2);
@@ -13561,12 +13601,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1356113601
case RISCVISD::STRICT_VFNMADD_VL:
1356213602
case RISCVISD::STRICT_VFMSUB_VL:
1356313603
case RISCVISD::STRICT_VFNMSUB_VL:
13564-
return performVFMADD_VLCombine(N, DAG);
13604+
return performVFMADD_VLCombine(N, DAG, Subtarget);
1356513605
case RISCVISD::FMUL_VL:
13566-
return performVFMUL_VLCombine(N, DAG);
13606+
return performVFMUL_VLCombine(N, DAG, Subtarget);
1356713607
case RISCVISD::FADD_VL:
1356813608
case RISCVISD::FSUB_VL:
13569-
return performFADDSUB_VLCombine(N, DAG);
13609+
return performFADDSUB_VLCombine(N, DAG, Subtarget);
1357013610
case ISD::LOAD:
1357113611
case ISD::STORE: {
1357213612
if (DCI.isAfterLegalizeDAG())

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5870,11 +5870,13 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction> {
58705870
foreach fvtiToFWti = AllWidenableFloatVectors in {
58715871
defvar fvti = fvtiToFWti.Vti;
58725872
defvar fwti = fvtiToFWti.Wti;
5873-
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
5874-
GetVTypePredicates<fwti>.Predicates) in
5875-
defm : VPatConversionTA<intrinsic, instruction, "V",
5876-
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5877-
fvti.LMul, fwti.RegClass, fvti.RegClass>;
5873+
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
5874+
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
5875+
!listconcat(GetVTypePredicates<fvti>.Predicates,
5876+
GetVTypePredicates<fwti>.Predicates)) in
5877+
defm : VPatConversionTA<intrinsic, instruction, "V",
5878+
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5879+
fvti.LMul, fwti.RegClass, fvti.RegClass>;
58785880
}
58795881
}
58805882

@@ -5939,8 +5941,9 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
59395941
}
59405942
}
59415943

5942-
multiclass VPatConversionVF_WF_RM <string intrinsic, string instruction> {
5943-
foreach fvtiToFWti = AllWidenableFloatVectors in {
5944+
multiclass VPatConversionVF_WF_RM <string intrinsic, string instruction,
5945+
list<VTypeInfoToWide> wlist = AllWidenableFloatVectors> {
5946+
foreach fvtiToFWti = wlist in {
59445947
defvar fvti = fvtiToFWti.Vti;
59455948
defvar fwti = fvtiToFWti.Wti;
59465949
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
@@ -7196,8 +7199,17 @@ defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F
71967199
defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
71977200
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
71987201
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
7199-
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
7200-
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
7202+
defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
7203+
!ne(fvtiToFWti.Vti.Scalar, f16));
7204+
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7205+
WidenableFloatVectorsExceptF16>;
7206+
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
7207+
defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
7208+
!eq(fvtiToFWti.Vti.Scalar, f16));
7209+
let Predicates = [HasVInstructionsF16Minimal] in
7210+
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7211+
F16WidenableFloatVectors>;
7212+
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
72017213
"PseudoVFNCVTBF16_F_F">;
72027214
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
72037215

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1401,8 +1401,9 @@ defm : VPatNConvertI2FPSDNode_W_RM<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
14011401
foreach fvtiToFWti = AllWidenableFloatVectors in {
14021402
defvar fvti = fvtiToFWti.Vti;
14031403
defvar fwti = fvtiToFWti.Wti;
1404-
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
1405-
GetVTypePredicates<fwti>.Predicates) in
1404+
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
1405+
!listconcat(GetVTypePredicates<fvti>.Predicates,
1406+
GetVTypePredicates<fwti>.Predicates)) in
14061407
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
14071408
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
14081409
(fvti.Vector (IMPLICIT_DEF)),

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2589,8 +2589,9 @@ defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
25892589
foreach fvtiToFWti = AllWidenableFloatVectors in {
25902590
defvar fvti = fvtiToFWti.Vti;
25912591
defvar fwti = fvtiToFWti.Wti;
2592-
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
2593-
GetVTypePredicates<fwti>.Predicates) in
2592+
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
2593+
!listconcat(GetVTypePredicates<fvti>.Predicates,
2594+
GetVTypePredicates<fwti>.Predicates)) in
25942595
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
25952596
(fvti.Vector fvti.RegClass:$rs1),
25962597
(fvti.Mask V0),
@@ -2619,8 +2620,10 @@ defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">;
26192620
foreach fvtiToFWti = AllWidenableFloatVectors in {
26202621
defvar fvti = fvtiToFWti.Vti;
26212622
defvar fwti = fvtiToFWti.Wti;
2622-
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
2623-
GetVTypePredicates<fwti>.Predicates) in {
2623+
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
2624+
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
2625+
!listconcat(GetVTypePredicates<fvti>.Predicates,
2626+
GetVTypePredicates<fwti>.Predicates)) in {
26242627
def : Pat<(fvti.Vector (any_riscv_fpround_vl
26252628
(fwti.Vector fwti.RegClass:$rs1),
26262629
(fwti.Mask V0), VLOpFrag)),
@@ -2632,6 +2635,8 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
26322635
FRM_DYN,
26332636
GPR:$vl, fvti.Log2SEW, TA_MA)>;
26342637

2638+
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
2639+
GetVTypePredicates<fwti>.Predicates) in
26352640
def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl
26362641
(fwti.Vector fwti.RegClass:$rs1),
26372642
(fwti.Mask V0), VLOpFrag)),

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
166166
// Vector codegen related methods.
167167
bool hasVInstructions() const { return HasStdExtZve32x; }
168168
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
169+
bool hasVInstructionsF16Minimal() const {
170+
return HasStdExtZvfhmin || HasStdExtZvfh;
171+
}
169172
bool hasVInstructionsF16() const { return HasStdExtZvfh; }
170173
bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
171174
bool hasVInstructionsF32() const { return HasStdExtZve32f; }

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
33
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
5+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
46

57
declare <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half>, <2 x i1>, i32)
68

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
33
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
5+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
6+
47

58
declare <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float>, <2 x i1>, i32)
69

‎llvm/test/CodeGen/RISCV/rvv/vfadd.ll

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,12 @@
77
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
88
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \
99
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
10+
; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
11+
; RUN: -target-abi=ilp32d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
12+
; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
13+
; RUN: -target-abi=lp64d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
14+
15+
; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd
1016

1117
declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
1218
<vscale x 1 x half>,

‎llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,10 @@
33
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
55
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
6-
6+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
7+
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
8+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
9+
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
710
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
811
<vscale x 1 x half>,
912
<vscale x 1 x float>,

‎llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
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;

‎llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
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declare <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
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‎llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
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;

‎llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
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declare <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
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‎llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll

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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
6-
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
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declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
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<vscale x 1 x float>,
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<vscale x 1 x half>,

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