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[PowerPC] Fix vperm codegen
Commit rG934d5fa2b8672695c335deed0e19d0e777c98403 changed the vperm codegen for cases that vperm is not replaced by xxperm, this patch is to revert that. Reviewed By: stefanp Differential Revision: https://reviews.llvm.org/D138736
1 parent ca856ff commit 7614ba0

13 files changed

+140
-131
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 32 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -10186,9 +10186,6 @@ SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
1018610186
}
1018710187
}
1018810188

10189-
bool V1HasXXSWAPD = V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
10190-
bool V2HasXXSWAPD = V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
10191-
1019210189
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1019310190
// that it is in input element units, not in bytes. Convert now.
1019410191

@@ -10199,6 +10196,9 @@ SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
1019910196
EVT EltVT = V1.getValueType().getVectorElementType();
1020010197
unsigned BytesPerElement = EltVT.getSizeInBits() / 8;
1020110198

10199+
bool V1HasXXSWAPD = V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
10200+
bool V2HasXXSWAPD = V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
10201+
1020210202
/*
1020310203
Vectors will be appended like so: [ V1 | v2 ]
1020410204
XXSWAPD on V1:
@@ -10219,24 +10219,27 @@ SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
1021910219
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
1022010220
unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
1022110221

10222-
if (V1HasXXSWAPD) {
10223-
if (SrcElt < 8)
10224-
SrcElt += 8;
10225-
else if (SrcElt < 16)
10226-
SrcElt -= 8;
10227-
}
10228-
if (V2HasXXSWAPD) {
10229-
if (SrcElt > 23)
10230-
SrcElt -= 8;
10231-
else if (SrcElt > 15)
10232-
SrcElt += 8;
10233-
}
10234-
if (NeedSwap) {
10235-
if (SrcElt < 16)
10236-
SrcElt += 16;
10237-
else
10238-
SrcElt -= 16;
10222+
if (Opcode == PPCISD::XXPERM) {
10223+
if (V1HasXXSWAPD) {
10224+
if (SrcElt < 8)
10225+
SrcElt += 8;
10226+
else if (SrcElt < 16)
10227+
SrcElt -= 8;
10228+
}
10229+
if (V2HasXXSWAPD) {
10230+
if (SrcElt > 23)
10231+
SrcElt -= 8;
10232+
else if (SrcElt > 15)
10233+
SrcElt += 8;
10234+
}
10235+
if (NeedSwap) {
10236+
if (SrcElt < 16)
10237+
SrcElt += 16;
10238+
else
10239+
SrcElt -= 16;
10240+
}
1023910241
}
10242+
1024010243
for (unsigned j = 0; j != BytesPerElement; ++j)
1024110244
if (isLittleEndian)
1024210245
ResultMask.push_back(
@@ -10246,16 +10249,15 @@ SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
1024610249
DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32));
1024710250
}
1024810251

10249-
if (V1HasXXSWAPD) {
10250-
dl = SDLoc(V1->getOperand(0));
10251-
V1 = V1->getOperand(0)->getOperand(1);
10252-
}
10253-
if (V2HasXXSWAPD) {
10254-
dl = SDLoc(V2->getOperand(0));
10255-
V2 = V2->getOperand(0)->getOperand(1);
10256-
}
10257-
10258-
if (V1HasXXSWAPD || V2HasXXSWAPD || Opcode == PPCISD::XXPERM) {
10252+
if (Opcode == PPCISD::XXPERM && (V1HasXXSWAPD || V2HasXXSWAPD)) {
10253+
if (V1HasXXSWAPD) {
10254+
dl = SDLoc(V1->getOperand(0));
10255+
V1 = V1->getOperand(0)->getOperand(1);
10256+
}
10257+
if (V2HasXXSWAPD) {
10258+
dl = SDLoc(V2->getOperand(0));
10259+
V2 = V2->getOperand(0)->getOperand(1);
10260+
}
1025910261
if (isPPC64 && ValType != MVT::v2f64)
1026010262
V1 = DAG.getBitcast(MVT::v2f64, V1);
1026110263
if (isPPC64 && V2.getValueType() != MVT::v2f64)

‎llvm/test/CodeGen/PowerPC/build-vector-tests.ll

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,14 +1058,15 @@ define <4 x i32> @fromDiffMemVarDi(ptr nocapture readonly %arr, i32 signext %ele
10581058
;
10591059
; P8LE-LABEL: fromDiffMemVarDi:
10601060
; P8LE: # %bb.0: # %entry
1061-
; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
10621061
; P8LE-NEXT: sldi r4, r4, 2
1063-
; P8LE-NEXT: addi r5, r5, .LCPI9_0@toc@l
1062+
; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
10641063
; P8LE-NEXT: add r3, r3, r4
1065-
; P8LE-NEXT: lxvd2x vs0, 0, r5
1064+
; P8LE-NEXT: addi r4, r5, .LCPI9_0@toc@l
10661065
; P8LE-NEXT: addi r3, r3, -12
1067-
; P8LE-NEXT: lxvd2x v2, 0, r3
1068-
; P8LE-NEXT: xxswapd v3, vs0
1066+
; P8LE-NEXT: lxvd2x vs1, 0, r4
1067+
; P8LE-NEXT: lxvd2x vs0, 0, r3
1068+
; P8LE-NEXT: xxswapd v3, vs1
1069+
; P8LE-NEXT: xxswapd v2, vs0
10691070
; P8LE-NEXT: vperm v2, v2, v2, v3
10701071
; P8LE-NEXT: blr
10711072
entry:
@@ -1478,10 +1479,11 @@ define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) {
14781479
; P8LE-LABEL: fromDiffMemConsDConvftoi:
14791480
; P8LE: # %bb.0: # %entry
14801481
; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
1481-
; P8LE-NEXT: lxvd2x v2, 0, r3
1482+
; P8LE-NEXT: lxvd2x vs0, 0, r3
14821483
; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l
1483-
; P8LE-NEXT: lxvd2x vs0, 0, r4
1484-
; P8LE-NEXT: xxswapd v3, vs0
1484+
; P8LE-NEXT: lxvd2x vs1, 0, r4
1485+
; P8LE-NEXT: xxswapd v2, vs0
1486+
; P8LE-NEXT: xxswapd v3, vs1
14851487
; P8LE-NEXT: vperm v2, v2, v2, v3
14861488
; P8LE-NEXT: xvcvspsxws v2, v2
14871489
; P8LE-NEXT: blr
@@ -2578,14 +2580,15 @@ define <4 x i32> @fromDiffMemVarDui(ptr nocapture readonly %arr, i32 signext %el
25782580
;
25792581
; P8LE-LABEL: fromDiffMemVarDui:
25802582
; P8LE: # %bb.0: # %entry
2581-
; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
25822583
; P8LE-NEXT: sldi r4, r4, 2
2583-
; P8LE-NEXT: addi r5, r5, .LCPI41_0@toc@l
2584+
; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
25842585
; P8LE-NEXT: add r3, r3, r4
2585-
; P8LE-NEXT: lxvd2x vs0, 0, r5
2586+
; P8LE-NEXT: addi r4, r5, .LCPI41_0@toc@l
25862587
; P8LE-NEXT: addi r3, r3, -12
2587-
; P8LE-NEXT: lxvd2x v2, 0, r3
2588-
; P8LE-NEXT: xxswapd v3, vs0
2588+
; P8LE-NEXT: lxvd2x vs1, 0, r4
2589+
; P8LE-NEXT: lxvd2x vs0, 0, r3
2590+
; P8LE-NEXT: xxswapd v3, vs1
2591+
; P8LE-NEXT: xxswapd v2, vs0
25892592
; P8LE-NEXT: vperm v2, v2, v2, v3
25902593
; P8LE-NEXT: blr
25912594
entry:
@@ -2998,10 +3001,11 @@ define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) {
29983001
; P8LE-LABEL: fromDiffMemConsDConvftoui:
29993002
; P8LE: # %bb.0: # %entry
30003003
; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
3001-
; P8LE-NEXT: lxvd2x v2, 0, r3
3004+
; P8LE-NEXT: lxvd2x vs0, 0, r3
30023005
; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l
3003-
; P8LE-NEXT: lxvd2x vs0, 0, r4
3004-
; P8LE-NEXT: xxswapd v3, vs0
3006+
; P8LE-NEXT: lxvd2x vs1, 0, r4
3007+
; P8LE-NEXT: xxswapd v2, vs0
3008+
; P8LE-NEXT: xxswapd v3, vs1
30053009
; P8LE-NEXT: vperm v2, v2, v2, v3
30063010
; P8LE-NEXT: xvcvspuxws v2, v2
30073011
; P8LE-NEXT: blr

‎llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -491,10 +491,10 @@ define dso_local <8 x i16> @testmrglb3(ptr nocapture readonly %a) local_unnamed_
491491
; CHECK-P9-BE: # %bb.0: # %entry
492492
; CHECK-P9-BE-NEXT: lxsd v2, 0(r3)
493493
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI12_0@toc@ha
494-
; CHECK-P9-BE-NEXT: xxlxor vs0, vs0, vs0
494+
; CHECK-P9-BE-NEXT: xxlxor vs1, vs1, vs1
495495
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI12_0@toc@l
496-
; CHECK-P9-BE-NEXT: lxv vs1, 0(r3)
497-
; CHECK-P9-BE-NEXT: xxperm v2, vs0, vs1
496+
; CHECK-P9-BE-NEXT: lxv vs0, 0(r3)
497+
; CHECK-P9-BE-NEXT: xxperm v2, vs1, vs0
498498
; CHECK-P9-BE-NEXT: blr
499499
;
500500
; CHECK-NOVSX-LABEL: testmrglb3:

‎llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,11 @@ define dso_local <4 x i16> @shufflevector_combine(<4 x i32> %0) #0 {
6666
; BE-LABEL: shufflevector_combine:
6767
; BE: # %bb.0: # %newFuncRoot
6868
; BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
69-
; BE-NEXT: xxlxor vs0, vs0, vs0
69+
; BE-NEXT: xxlxor vs1, vs1, vs1
7070
; BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
71-
; BE-NEXT: lxv vs1, 0(r3)
71+
; BE-NEXT: lxv vs0, 0(r3)
7272
; BE-NEXT: li r3, 0
73-
; BE-NEXT: xxperm v2, vs0, vs1
73+
; BE-NEXT: xxperm v2, vs1, vs0
7474
; BE-NEXT: vinsw v2, r3, 8
7575
; BE-NEXT: vpkuwum v2, v2, v2
7676
; BE-NEXT: blr

‎llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -44,15 +44,15 @@ define void @test64(ptr nocapture readonly %pix2, i32 signext %i_pix2) {
4444
; P9BE-NEXT: add 5, 3, 4
4545
; P9BE-NEXT: lxsdx 2, 3, 4
4646
; P9BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
47-
; P9BE-NEXT: xxlxor 0, 0, 0
47+
; P9BE-NEXT: xxlxor 1, 1, 1
4848
; P9BE-NEXT: vspltisw 4, 8
4949
; P9BE-NEXT: lxsd 3, 4(5)
5050
; P9BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
5151
; P9BE-NEXT: vadduwm 4, 4, 4
52-
; P9BE-NEXT: lxv 1, 0(3)
52+
; P9BE-NEXT: lxv 0, 0(3)
5353
; P9BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
5454
; P9BE-NEXT: addi 3, 3, .LCPI0_1@toc@l
55-
; P9BE-NEXT: xxperm 2, 0, 1
55+
; P9BE-NEXT: xxperm 2, 1, 0
5656
; P9BE-NEXT: lxv 0, 0(3)
5757
; P9BE-NEXT: xxperm 3, 3, 0
5858
; P9BE-NEXT: vnegw 3, 3
@@ -285,10 +285,10 @@ define void @test16(ptr nocapture readonly %sums, i32 signext %delta, i32 signex
285285
; P9BE-NEXT: addis 3, 2, .LCPI2_1@toc@ha
286286
; P9BE-NEXT: addi 3, 3, .LCPI2_1@toc@l
287287
; P9BE-NEXT: xxperm 2, 0, 1
288-
; P9BE-NEXT: lxv 1, 0(3)
288+
; P9BE-NEXT: lxv 0, 0(3)
289289
; P9BE-NEXT: li 3, 0
290-
; P9BE-NEXT: xxmrghw 0, 4, 2
291-
; P9BE-NEXT: xxperm 3, 0, 1
290+
; P9BE-NEXT: xxmrghw 2, 4, 2
291+
; P9BE-NEXT: xxperm 3, 2, 0
292292
; P9BE-NEXT: xxspltw 2, 3, 1
293293
; P9BE-NEXT: vadduwm 2, 3, 2
294294
; P9BE-NEXT: vextuwlx 3, 3, 2
@@ -312,10 +312,10 @@ define void @test16(ptr nocapture readonly %sums, i32 signext %delta, i32 signex
312312
; P9BE-AIX-NEXT: lxsihzx 0, 3, 4
313313
; P9BE-AIX-NEXT: ld 3, L..C4(2) # %const.1
314314
; P9BE-AIX-NEXT: xxperm 2, 0, 1
315-
; P9BE-AIX-NEXT: lxv 1, 0(3)
315+
; P9BE-AIX-NEXT: lxv 0, 0(3)
316316
; P9BE-AIX-NEXT: li 3, 0
317-
; P9BE-AIX-NEXT: xxmrghw 0, 4, 2
318-
; P9BE-AIX-NEXT: xxperm 3, 0, 1
317+
; P9BE-AIX-NEXT: xxmrghw 2, 4, 2
318+
; P9BE-AIX-NEXT: xxperm 3, 2, 0
319319
; P9BE-AIX-NEXT: xxspltw 2, 3, 1
320320
; P9BE-AIX-NEXT: vadduwm 2, 3, 2
321321
; P9BE-AIX-NEXT: vextuwlx 3, 3, 2
@@ -395,13 +395,13 @@ define void @test8(ptr nocapture readonly %sums, i32 signext %delta, i32 signext
395395
; P9LE-NEXT: vmrghb 2, 3, 2
396396
; P9LE-NEXT: addi 3, 3, .LCPI3_0@toc@l
397397
; P9LE-NEXT: vmrglh 2, 2, 4
398-
; P9LE-NEXT: lxv 1, 0(3)
398+
; P9LE-NEXT: lxv 0, 0(3)
399399
; P9LE-NEXT: li 3, 0
400400
; P9LE-NEXT: vmrghb 3, 3, 5
401401
; P9LE-NEXT: xxmrglw 2, 2, 4
402402
; P9LE-NEXT: vmrglh 3, 3, 4
403-
; P9LE-NEXT: xxmrglw 0, 4, 3
404-
; P9LE-NEXT: xxperm 2, 0, 1
403+
; P9LE-NEXT: xxmrglw 3, 4, 3
404+
; P9LE-NEXT: xxperm 2, 3, 0
405405
; P9LE-NEXT: xxspltw 3, 2, 2
406406
; P9LE-NEXT: vadduwm 2, 2, 3
407407
; P9LE-NEXT: vextuwrx 3, 3, 2

‎llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -184,11 +184,12 @@ define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) {
184184
; CHECK-LE-P8-LABEL: test_none_v16i8:
185185
; CHECK-LE-P8: # %bb.0: # %entry
186186
; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
187-
; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4
187+
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4
188188
; CHECK-LE-P8-NEXT: mtvsrd v4, r3
189189
; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
190-
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
191-
; CHECK-LE-P8-NEXT: xxswapd v3, vs0
190+
; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5
191+
; CHECK-LE-P8-NEXT: xxswapd v2, vs0
192+
; CHECK-LE-P8-NEXT: xxswapd v3, vs1
192193
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
193194
; CHECK-LE-P8-NEXT: blr
194195
;
@@ -431,11 +432,12 @@ define <16 x i8> @test_none_v8i16(i16 %arg, ptr nocapture noundef readonly %b) {
431432
; CHECK-LE-P8-LABEL: test_none_v8i16:
432433
; CHECK-LE-P8: # %bb.0: # %entry
433434
; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
434-
; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4
435+
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4
435436
; CHECK-LE-P8-NEXT: mtvsrd v4, r3
436437
; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
437-
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
438-
; CHECK-LE-P8-NEXT: xxswapd v3, vs0
438+
; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5
439+
; CHECK-LE-P8-NEXT: xxswapd v2, vs0
440+
; CHECK-LE-P8-NEXT: xxswapd v3, vs1
439441
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
440442
; CHECK-LE-P8-NEXT: blr
441443
;

‎llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -389,10 +389,10 @@ define void @test_v4i32_none(ptr nocapture readonly %ptr1, ptr nocapture readonl
389389
; CHECK-LE-P9: # %bb.0: # %entry
390390
; CHECK-LE-P9-NEXT: lfiwzx f0, 0, r3
391391
; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
392-
; CHECK-LE-P9-NEXT: xxlxor vs1, vs1, vs1
392+
; CHECK-LE-P9-NEXT: xxlxor vs2, vs2, vs2
393393
; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
394-
; CHECK-LE-P9-NEXT: lxv vs2, 0(r3)
395-
; CHECK-LE-P9-NEXT: xxperm vs0, vs1, vs2
394+
; CHECK-LE-P9-NEXT: lxv vs1, 0(r3)
395+
; CHECK-LE-P9-NEXT: xxperm vs0, vs2, vs1
396396
; CHECK-LE-P9-NEXT: stxv vs0, 0(r3)
397397
; CHECK-LE-P9-NEXT: blr
398398
;
@@ -411,10 +411,10 @@ define void @test_v4i32_none(ptr nocapture readonly %ptr1, ptr nocapture readonl
411411
; CHECK-BE-P9: # %bb.0: # %entry
412412
; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3
413413
; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
414-
; CHECK-BE-P9-NEXT: xxlxor vs1, vs1, vs1
414+
; CHECK-BE-P9-NEXT: xxlxor vs2, vs2, vs2
415415
; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
416-
; CHECK-BE-P9-NEXT: lxv vs2, 0(r3)
417-
; CHECK-BE-P9-NEXT: xxperm vs0, vs1, vs2
416+
; CHECK-BE-P9-NEXT: lxv vs1, 0(r3)
417+
; CHECK-BE-P9-NEXT: xxperm vs0, vs2, vs1
418418
; CHECK-BE-P9-NEXT: stxv vs0, 0(r3)
419419
; CHECK-BE-P9-NEXT: blr
420420
;
@@ -470,14 +470,15 @@ define void @test_none_v2i64(ptr nocapture readonly %ptr1, ptr nocapture readonl
470470
; CHECK-LE-P8-LABEL: test_none_v2i64:
471471
; CHECK-LE-P8: # %bb.0: # %entry
472472
; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI4_0@toc@ha
473+
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4
473474
; CHECK-LE-P8-NEXT: lxsdx v2, 0, r3
474-
; CHECK-LE-P8-NEXT: lxvd2x v3, 0, r4
475475
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
476476
; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI4_0@toc@l
477477
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
478-
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
479-
; CHECK-LE-P8-NEXT: xxswapd v4, vs0
478+
; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5
479+
; CHECK-LE-P8-NEXT: xxswapd v3, vs0
480480
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
481+
; CHECK-LE-P8-NEXT: xxswapd v4, vs1
481482
; CHECK-LE-P8-NEXT: vperm v2, v2, v3, v4
482483
; CHECK-LE-P8-NEXT: xxswapd v3, vs0
483484
; CHECK-LE-P8-NEXT: xxlxor v4, v4, v4
@@ -544,10 +545,10 @@ define void @test_none_v2i64(ptr nocapture readonly %ptr1, ptr nocapture readonl
544545
; CHECK-AIX-64-P9: # %bb.0: # %entry
545546
; CHECK-AIX-64-P9-NEXT: lxsd v2, 0(r3)
546547
; CHECK-AIX-64-P9-NEXT: ld r3, L..C5(r2) # %const.0
547-
; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r4)
548+
; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r4)
548549
; CHECK-AIX-64-P9-NEXT: xxlxor v3, v3, v3
549-
; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r3)
550-
; CHECK-AIX-64-P9-NEXT: xxperm v2, vs1, vs0
550+
; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3)
551+
; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1
551552
; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2
552553
; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3)
553554
; CHECK-AIX-64-P9-NEXT: blr
@@ -603,10 +604,10 @@ define void @test_v2i64_none(ptr nocapture readonly %ptr1) {
603604
; CHECK-LE-P9: # %bb.0: # %entry
604605
; CHECK-LE-P9-NEXT: lfd f0, 0(r3)
605606
; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
606-
; CHECK-LE-P9-NEXT: xxlxor vs1, vs1, vs1
607+
; CHECK-LE-P9-NEXT: xxlxor vs2, vs2, vs2
607608
; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
608-
; CHECK-LE-P9-NEXT: lxv vs2, 0(r3)
609-
; CHECK-LE-P9-NEXT: xxperm vs0, vs1, vs2
609+
; CHECK-LE-P9-NEXT: lxv vs1, 0(r3)
610+
; CHECK-LE-P9-NEXT: xxperm vs0, vs2, vs1
610611
; CHECK-LE-P9-NEXT: stxv vs0, 0(r3)
611612
; CHECK-LE-P9-NEXT: blr
612613
;
@@ -625,10 +626,10 @@ define void @test_v2i64_none(ptr nocapture readonly %ptr1) {
625626
; CHECK-BE-P9: # %bb.0: # %entry
626627
; CHECK-BE-P9-NEXT: lfd f0, 0(r3)
627628
; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
628-
; CHECK-BE-P9-NEXT: xxlxor vs1, vs1, vs1
629+
; CHECK-BE-P9-NEXT: xxlxor vs2, vs2, vs2
629630
; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
630-
; CHECK-BE-P9-NEXT: lxv vs2, 0(r3)
631-
; CHECK-BE-P9-NEXT: xxperm vs0, vs1, vs2
631+
; CHECK-BE-P9-NEXT: lxv vs1, 0(r3)
632+
; CHECK-BE-P9-NEXT: xxperm vs0, vs2, vs1
632633
; CHECK-BE-P9-NEXT: stxv vs0, 0(r3)
633634
; CHECK-BE-P9-NEXT: blr
634635
;

‎llvm/test/CodeGen/PowerPC/vec-itofp.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -203,13 +203,13 @@ define void @test2(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
203203
;
204204
; CHECK-P9-LABEL: test2:
205205
; CHECK-P9: # %bb.0: # %entry
206-
; CHECK-P9-NEXT: lxv vs1, 0(r4)
206+
; CHECK-P9-NEXT: lxv vs0, 0(r4)
207207
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
208-
; CHECK-P9-NEXT: xxlxor vs0, vs0, vs0
208+
; CHECK-P9-NEXT: xxlxor vs2, vs2, vs2
209209
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
210-
; CHECK-P9-NEXT: lxv vs2, 0(r4)
211-
; CHECK-P9-NEXT: xxperm vs1, vs0, vs2
212-
; CHECK-P9-NEXT: xvcvuxddp vs0, vs1
210+
; CHECK-P9-NEXT: lxv vs1, 0(r4)
211+
; CHECK-P9-NEXT: xxperm vs0, vs2, vs1
212+
; CHECK-P9-NEXT: xvcvuxddp vs0, vs0
213213
; CHECK-P9-NEXT: stxv vs0, 0(r3)
214214
; CHECK-P9-NEXT: blr
215215
;

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