@@ -1639,22 +1639,22 @@ defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
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let Predicates = [HasAVX] in {
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def : Pat<(int_x86_sse_cvtss2si VR128:$src),
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- (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss ))>;
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+ (VCVTSS2SIrr (COPY_TO_REGCLASS VR128:$src, FR32 ))>;
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def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
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(VCVTSS2SIrm addr:$src)>;
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def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
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- (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss ))>;
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+ (VCVTSS2SI64rr (COPY_TO_REGCLASS VR128:$src, FR32 ))>;
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def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
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(VCVTSS2SI64rm addr:$src)>;
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}
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let Predicates = [HasSSE1] in {
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def : Pat<(int_x86_sse_cvtss2si VR128:$src),
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- (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss ))>;
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+ (CVTSS2SIrr (COPY_TO_REGCLASS VR128:$src, FR32 ))>;
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def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
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(CVTSS2SIrm addr:$src)>;
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def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
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- (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss ))>;
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+ (CVTSS2SI64rr (COPY_TO_REGCLASS VR128:$src, FR32 ))>;
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def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
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(CVTSS2SI64rm addr:$src)>;
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}
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