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Merge pull request #3627 from bnbarham/cherry-missing-commits
[stable/20211026] Cherry-pick missing commits
2 parents 942865f + 257c95b commit 78ddf27

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‎clang/include/clang/AST/DeclContextInternals.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,11 @@ class StoredDeclsList {
237237

238238
// FIXME: Move the assert before the single decl case when we fix the
239239
// duplication coming from the ASTReader reading builtin types.
240-
assert(!llvm::is_contained(getLookupResult(), D) && "Already exists!");
240+
241+
// SWIFT: FIXME^2: This assertion causes problems in Swift's ClangImporter.
242+
// SWIFT: We should probably set its ASTContext to Objective-C++ mode to avoid it.
243+
// SWIFT: assert(!llvm::is_contained(getLookupResult(), D) && "Already exists!");
244+
241245
// Determine if this declaration is actually a redeclaration.
242246
for (DeclListNode *N = getAsList(); /*return in loop*/;
243247
N = N->Rest.dyn_cast<DeclListNode *>()) {

‎clang/include/clang/Serialization/ASTReader.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,10 +1155,6 @@ class ASTReader
11551155
/// definitions. Only populated when using modules in C++.
11561156
llvm::DenseMap<EnumDecl *, EnumDecl *> EnumDefinitions;
11571157

1158-
/// A mapping from canonical declarations of records to their canonical
1159-
/// definitions. Doesn't cover CXXRecordDecl.
1160-
llvm::DenseMap<RecordDecl *, RecordDecl *> RecordDefinitions;
1161-
11621158
/// When reading a Stmt tree, Stmt operands are placed in this stack.
11631159
SmallVector<Stmt *, 16> StmtStack;
11641160

‎clang/lib/Headers/CMakeLists.txt

Lines changed: 18 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -207,20 +207,24 @@ foreach( f ${files} ${cuda_wrapper_files} ${ppc_wrapper_files} ${openmp_wrapper_
207207
endforeach( f )
208208

209209
# Generate header files and copy them to the build directory
210-
# Generate arm_neon.h
211-
clang_generate_header(-gen-arm-neon arm_neon.td arm_neon.h)
212-
# Generate arm_fp16.h
213-
clang_generate_header(-gen-arm-fp16 arm_fp16.td arm_fp16.h)
214-
# Generate arm_sve.h
215-
clang_generate_header(-gen-arm-sve-header arm_sve.td arm_sve.h)
216-
# Generate arm_bf16.h
217-
clang_generate_header(-gen-arm-bf16 arm_bf16.td arm_bf16.h)
218-
# Generate arm_mve.h
219-
clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
220-
# Generate arm_cde.h
221-
clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h)
222-
# Generate riscv_vector.h
223-
clang_generate_header(-gen-riscv-vector-header riscv_vector.td riscv_vector.h)
210+
if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST LLVM_TARGETS_TO_BUILD)
211+
# Generate arm_neon.h
212+
clang_generate_header(-gen-arm-neon arm_neon.td arm_neon.h)
213+
# Generate arm_fp16.h
214+
clang_generate_header(-gen-arm-fp16 arm_fp16.td arm_fp16.h)
215+
# Generate arm_sve.h
216+
clang_generate_header(-gen-arm-sve-header arm_sve.td arm_sve.h)
217+
# Generate arm_bf16.h
218+
clang_generate_header(-gen-arm-bf16 arm_bf16.td arm_bf16.h)
219+
# Generate arm_mve.h
220+
clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
221+
# Generate arm_cde.h
222+
clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h)
223+
endif()
224+
if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD)
225+
# Generate riscv_vector.h
226+
clang_generate_header(-gen-riscv-vector-header riscv_vector.td riscv_vector.h)
227+
endif()
224228

225229
add_custom_target(clang-resource-headers ALL DEPENDS ${out_files})
226230
set_target_properties(clang-resource-headers PROPERTIES

‎clang/lib/Serialization/ASTCommon.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,7 @@ bool serialization::needsAnonymousDeclarationNumber(const NamedDecl *D) {
477477
// Otherwise, we only care about anonymous class members / block-scope decls.
478478
// FIXME: We need to handle lambdas and blocks within inline / templated
479479
// variables too.
480-
if (D->getDeclName() || !isa<RecordDecl>(D->getLexicalDeclContext()))
480+
if (D->getDeclName() || !isa<CXXRecordDecl>(D->getLexicalDeclContext()))
481481
return false;
482482
return isa<TagDecl>(D) || isa<FieldDecl>(D);
483483
}

‎clang/lib/Serialization/ASTReaderDecl.cpp

Lines changed: 2 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,7 @@ namespace clang {
332332
RedeclarableResult VisitTagDecl(TagDecl *TD);
333333
void VisitEnumDecl(EnumDecl *ED);
334334
RedeclarableResult VisitRecordDeclImpl(RecordDecl *RD);
335-
void VisitRecordDecl(RecordDecl *RD);
335+
void VisitRecordDecl(RecordDecl *RD) { VisitRecordDeclImpl(RD); }
336336
RedeclarableResult VisitCXXRecordDeclImpl(CXXRecordDecl *D);
337337
void VisitCXXRecordDecl(CXXRecordDecl *D) { VisitCXXRecordDeclImpl(D); }
338338
RedeclarableResult VisitClassTemplateSpecializationDeclImpl(
@@ -808,34 +808,6 @@ ASTDeclReader::VisitRecordDeclImpl(RecordDecl *RD) {
808808
return Redecl;
809809
}
810810

811-
void ASTDeclReader::VisitRecordDecl(RecordDecl *RD) {
812-
VisitRecordDeclImpl(RD);
813-
814-
// Maintain the invariant of a redeclaration chain containing only
815-
// a single definition.
816-
if (RD->isCompleteDefinition()) {
817-
RecordDecl *Canon = static_cast<RecordDecl *>(RD->getCanonicalDecl());
818-
RecordDecl *&OldDef = Reader.RecordDefinitions[Canon];
819-
if (!OldDef) {
820-
// This is the first time we've seen an imported definition. Look for a
821-
// local definition before deciding that we are the first definition.
822-
for (auto *D : merged_redecls(Canon)) {
823-
if (!D->isFromASTFile() && D->isCompleteDefinition()) {
824-
OldDef = D;
825-
break;
826-
}
827-
}
828-
}
829-
if (OldDef) {
830-
Reader.MergedDeclContexts.insert(std::make_pair(RD, OldDef));
831-
RD->setCompleteDefinition(false);
832-
Reader.mergeDefinitionVisibility(OldDef, RD);
833-
} else {
834-
OldDef = RD;
835-
}
836-
}
837-
}
838-
839811
void ASTDeclReader::VisitValueDecl(ValueDecl *VD) {
840812
VisitNamedDecl(VD);
841813
// For function declarations, defer reading the type in case the function has
@@ -2689,7 +2661,7 @@ static bool allowODRLikeMergeInC(NamedDecl *ND) {
26892661
if (!ND)
26902662
return false;
26912663
// TODO: implement merge for other necessary decls.
2692-
if (isa<EnumConstantDecl, FieldDecl, IndirectFieldDecl>(ND))
2664+
if (isa<EnumConstantDecl>(ND))
26932665
return true;
26942666
return false;
26952667
}
@@ -3361,9 +3333,6 @@ DeclContext *ASTDeclReader::getPrimaryContextForMerging(ASTReader &Reader,
33613333
return DD->Definition;
33623334
}
33633335

3364-
if (auto *RD = dyn_cast<RecordDecl>(DC))
3365-
return RD->getDefinition();
3366-
33673336
if (auto *ED = dyn_cast<EnumDecl>(DC))
33683337
return ED->getASTContext().getLangOpts().CPlusPlus? ED->getDefinition()
33693338
: nullptr;
@@ -3450,9 +3419,6 @@ ASTDeclReader::getPrimaryDCForAnonymousDecl(DeclContext *LexicalDC) {
34503419
if (auto *MD = dyn_cast<ObjCMethodDecl>(D))
34513420
if (MD->isThisDeclarationADefinition())
34523421
return MD;
3453-
if (auto *RD = dyn_cast<RecordDecl>(D))
3454-
if (RD->isThisDeclarationADefinition())
3455-
return RD;
34563422
}
34573423

34583424
// No merged definition yet.

‎clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
// REQUIRES: riscv-registered-target
2+
13
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \
24
// RUN: -O2 -emit-llvm %s -o - \
35
// RUN: | FileCheck %s

‎clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
33
// RUN: -disable-O0-optnone -emit-llvm -fno-legacy-pass-manager %s -o - | opt -S -mem2reg | FileCheck %s
44

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
57
#include <arm_neon.h>
68

79
// CHECK-LABEL: @test_vbfdot_f32(

‎clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
33
// RUN: -disable-O0-optnone -emit-llvm -fno-legacy-pass-manager %s -o - | opt -S -mem2reg | FileCheck %s
44

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
57
#include <arm_neon.h>
68

79
// CHECK-LABEL: @test_vcreate_bf16(

‎clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
// RUN: %clang_cc1 -triple aarch64_be-arm-none-eabi -target-feature +neon -target-feature +bf16 \
55
// RUN: -disable-O0-optnone -emit-llvm %s -fno-legacy-pass-manager -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-BE %s
66

7+
// REQUIRES: aarch64-registered-target || arm-registered-target
8+
79
#include <arm_neon.h>
810

911
// CHECK-LE-LABEL: @test_vcopy_lane_bf16_v1(

‎clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
// REQUIRES: aarch64-registered-target
2-
31
// RUN: %clang -O3 -target aarch64-linux-eabi %s -S -o- \
42
// RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s
53
// RUN: %clang -O3 -target aarch64-linux-eabi -mfix-cortex-a53-835769 %s -S -o- 2>&1 \
@@ -14,6 +12,8 @@
1412
// RUN: %clang -O3 -target aarch64-android-eabi -mno-fix-cortex-a53-835769 %s -S -o- \
1513
// RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s
1614

15+
// REQUIRES: aarch64-registered-target
16+
1717
typedef long int64_t;
1818

1919
int64_t f_load_madd_64(int64_t a, int64_t b, int64_t *c) {

‎clang/test/CodeGen/aarch64-neon-2velem.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
22
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
55

66
#include <arm_neon.h>
77

‎clang/test/CodeGen/aarch64-neon-3v.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
22

3-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
44

55
#include <arm_neon.h>
66

‎clang/test/CodeGen/aarch64-neon-across.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
55

66
#include <arm_neon.h>
77

‎clang/test/CodeGen/aarch64-neon-extract.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
// REQUIRES: aarch64-registered-target
21
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
32
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
43

5-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target
65

76
#include <arm_neon.h>
87

‎clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
55

66
#include <arm_neon.h>
77

‎clang/test/CodeGen/aarch64-neon-fma.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
22

3-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
44

55
#include <arm_neon.h>
66

‎clang/test/CodeGen/aarch64-neon-intrinsics.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// RUN: | opt -S -mem2reg \
55
// RUN: | FileCheck %s
66

7-
// Test new aarch64 intrinsics and types
7+
// REQUIRES: aarch64-registered-target || arm-registered-target
88

99
#include <arm_neon.h>
1010

‎clang/test/CodeGen/aarch64-neon-ldst-one.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
33
// RUN: | opt -S -mem2reg | FileCheck %s
44

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
57
#include <arm_neon.h>
68

79
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_u8(i8* %a) #0 {

‎clang/test/CodeGen/aarch64-neon-misc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
33
// RUN: | opt -S -mem2reg | FileCheck %s
44

5-
// Test new aarch64 intrinsics and types
5+
// REQUIRES: aarch64-registered-target || arm-registered-target
66

77
#include <arm_neon.h>
88

‎clang/test/CodeGen/aarch64-neon-perm.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
56
#include <arm_neon.h>
67

78
// CHECK-LABEL: @test_vuzp1_s8(

‎clang/test/CodeGen/aarch64-neon-range-checks.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -target-feature +sha3 -target-feature +sm4 -verify %s
22

3+
// REQUIRES: aarch64-registered-target || arm-registered-target
4+
35
#include <arm_neon.h>
46

57
void test_range_check_vsm3tt1a(uint32x4_t a, uint32x4_t b, uint32x4_t c) {

‎clang/test/CodeGen/aarch64-neon-scalar-copy.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
46
#include <arm_neon.h>
57

68
// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> %a) #0 {

‎clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
55

66
#include <arm_neon.h>
77

‎clang/test/CodeGen/aarch64-neon-sha3.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
// RUN: -target-feature +sha3 -S -emit-llvm -o - %s \
44
// RUN: | FileCheck %s
55

6+
// REQUIRES: aarch64-registered-target || arm-registered-target
7+
68
#include <arm_neon.h>
79

810
// CHECK-LABEL: @test_vsha512h(

‎clang/test/CodeGen/aarch64-neon-shifts.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
46
#include <arm_neon.h>
57

68
uint8x8_t test_shift_vshr(uint8x8_t a) {

‎clang/test/CodeGen/aarch64-neon-sm4-sm3.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
// RUN: not %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
66
// RUN: -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
77

8+
// REQUIRES: aarch64-registered-target || arm-registered-target
9+
810
#include <arm_neon.h>
911

1012
void test_vsm3partw1(uint32x4_t a, uint32x4_t b, uint32x4_t c) {

‎clang/test/CodeGen/aarch64-neon-tbl.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
22
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
33

4-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
55

66
#include <arm_neon.h>
77

‎clang/test/CodeGen/aarch64-neon-vcadd.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
// RUN: -target-feature +v8.3a -target-feature +fullfp16 -S -emit-llvm -o - %s \
33
// RUN: | FileCheck %s
44

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
57
#include <arm_neon.h>
68

79
void foo16x4_rot90(float16x4_t a, float16x4_t b)

‎clang/test/CodeGen/aarch64-neon-vcmla.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
1-
// REQUIRES: aarch64-registered-target
21
// RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon \
32
// RUN: -target-feature +v8.3a \
43
// RUN: -target-feature +fullfp16 \
54
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -O1 | FileCheck %s
5+
6+
// REQUIRES: aarch64-registered-target
7+
68
#include <arm_neon.h>
79

810
// CHECK-LABEL: @test_vcmla_f16(

‎clang/test/CodeGen/aarch64-neon-vcombine.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
22

3-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
44

55
#include <arm_neon.h>
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‎clang/test/CodeGen/aarch64-neon-vget-hilo.c

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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
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// RUN: | opt -S -mem2reg | FileCheck %s
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// Test new aarch64 intrinsics and types
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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‎clang/test/CodeGen/aarch64-neon-vget.c

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// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
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// RUN: | opt -S -mem2reg | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> %a) #0 {

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