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Merge commit '58f525a23ca4' from llvm.org/main into next
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‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,64 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
9090
ret {<2 x i64>, <2 x i64>} %retval
9191
}
9292

93+
define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
94+
; CHECK-LABEL: vector_deinterleave_v4i64_v8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v12
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; CHECK-NEXT: vadd.vv v14, v12, v12
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
101+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
102+
; CHECK-NEXT: vadd.vi v15, v14, -4
103+
; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
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; CHECK-NEXT: vslidedown.vi v16, v8, 4
106+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v12, v16, v15, v0.t
108+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v15, v14, 1
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v15
112+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v8, v14, -3
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
115+
; CHECK-NEXT: vrgatherei16.vv v10, v16, v8, v0.t
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; CHECK-NEXT: vmv.v.v v8, v12
117+
; CHECK-NEXT: ret
118+
%retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)
119+
ret {<4 x i64>, <4 x i64>} %retval
120+
}
121+
122+
define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec) {
123+
; CHECK-LABEL: vector_deinterleave_v8i64_v16i64:
124+
; CHECK: # %bb.0:
125+
; CHECK-NEXT: vmv8r.v v16, v8
126+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
127+
; CHECK-NEXT: vid.v v8
128+
; CHECK-NEXT: vadd.vv v7, v8, v8
129+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
130+
; CHECK-NEXT: vrgatherei16.vv v8, v16, v7
131+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
132+
; CHECK-NEXT: vmv.v.i v0, -16
133+
; CHECK-NEXT: vadd.vi v12, v7, -8
134+
; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
135+
; CHECK-NEXT: vslidedown.vi v24, v16, 8
136+
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
137+
; CHECK-NEXT: vrgatherei16.vv v8, v24, v12, v0.t
138+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
139+
; CHECK-NEXT: vadd.vi v20, v7, 1
140+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
141+
; CHECK-NEXT: vrgatherei16.vv v12, v16, v20
142+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
143+
; CHECK-NEXT: vadd.vi v16, v7, -7
144+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
145+
; CHECK-NEXT: vrgatherei16.vv v12, v24, v16, v0.t
146+
; CHECK-NEXT: ret
147+
%retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)
148+
ret {<8 x i64>, <8 x i64>} %retval
149+
}
150+
93151
declare {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1>)
94152
declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>)
95153
declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>)
@@ -176,9 +234,41 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double
176234
ret {<2 x double>, <2 x double>} %retval
177235
}
178236

237+
define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double> %vec) {
238+
; CHECK-LABEL: vector_deinterleave_v4f64_v8f64:
239+
; CHECK: # %bb.0:
240+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
241+
; CHECK-NEXT: vid.v v12
242+
; CHECK-NEXT: vadd.vv v14, v12, v12
243+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
244+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
245+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
246+
; CHECK-NEXT: vadd.vi v15, v14, -4
247+
; CHECK-NEXT: vmv.v.i v0, 12
248+
; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
249+
; CHECK-NEXT: vslidedown.vi v16, v8, 4
250+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
251+
; CHECK-NEXT: vrgatherei16.vv v12, v16, v15, v0.t
252+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
253+
; CHECK-NEXT: vadd.vi v15, v14, 1
254+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
255+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v15
256+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
257+
; CHECK-NEXT: vadd.vi v8, v14, -3
258+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
259+
; CHECK-NEXT: vrgatherei16.vv v10, v16, v8, v0.t
260+
; CHECK-NEXT: vmv.v.v v8, v12
261+
; CHECK-NEXT: ret
262+
%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)
263+
ret {<4 x double>, <4 x double>} %retval
264+
}
265+
179266
declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>)
180267
declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>)
181268
declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>)
182269
declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>)
183270
declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>)
184271
declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>)
272+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
273+
; RV32: {{.*}}
274+
; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,22 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
8484
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
8585
}
8686

87+
define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv8i64(<vscale x 8 x i64> %vec) {
88+
; CHECK-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
89+
; CHECK: # %bb.0:
90+
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
91+
; CHECK-NEXT: vid.v v16
92+
; CHECK-NEXT: vadd.vv v24, v16, v16
93+
; CHECK-NEXT: vrgather.vv v16, v8, v24
94+
; CHECK-NEXT: vadd.vi v24, v24, 1
95+
; CHECK-NEXT: vrgather.vv v0, v8, v24
96+
; CHECK-NEXT: vmv4r.v v8, v16
97+
; CHECK-NEXT: vmv4r.v v12, v0
98+
; CHECK-NEXT: ret
99+
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
100+
ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
101+
}
102+
87103
declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1>)
88104
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
89105
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)

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