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Merge commit '03861a267b26' from apple/master into swift/master-next
2 parents 7adf916 + 03861a2 commit 7cb5b6a

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6 files changed

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‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -599,9 +599,11 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
599599
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
600600
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
601601
case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
602+
case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
602603
case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
603604
case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
604605
case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
606+
case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
605607
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
606608
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
607609
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
@@ -665,6 +667,7 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
665667
switch (MI->getOpcode()) {
666668
default: break;
667669

670+
case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
668671
case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
669672
case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
670673
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 77 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -956,20 +956,24 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
956956
} // End DecoderNamespace = "SDWA10"
957957

958958
//===------------------------------ VOP2be ------------------------------===//
959-
multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> {
959+
multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
960960
def _e32_gfx10 :
961961
VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
962962
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
963963
VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
964964
let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
965965
}
966+
}
967+
multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
966968
def _e64_gfx10 :
967969
VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
968970
VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
969971
!cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
970972
VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
971973
let AsmString = asmName # Ps.AsmOperands;
972974
}
975+
}
976+
multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
973977
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
974978
def _sdwa_gfx10 :
975979
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
@@ -978,6 +982,28 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
978982
let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
979983
let DecoderNamespace = "SDWA10";
980984
}
985+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
986+
def _sdwa_w32_gfx10 :
987+
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
988+
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
989+
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
990+
let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
991+
let isAsmParserOnly = 1;
992+
let DecoderNamespace = "SDWA10";
993+
let WaveSizePredicate = isWave32;
994+
}
995+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
996+
def _sdwa_w64_gfx10 :
997+
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
998+
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
999+
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1000+
let AsmString = asmName # Ps.AsmOperands;
1001+
let isAsmParserOnly = 1;
1002+
let DecoderNamespace = "SDWA10";
1003+
let WaveSizePredicate = isWave64;
1004+
}
1005+
}
1006+
multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
9811007
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
9821008
def _dpp_gfx10 :
9831009
VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
@@ -986,60 +1012,46 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
9861012
let DecoderNamespace = "SDWA10";
9871013
}
9881014
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1015+
def _dpp_w32_gfx10 :
1016+
Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1017+
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1018+
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1019+
let isAsmParserOnly = 1;
1020+
let WaveSizePredicate = isWave32;
1021+
}
1022+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1023+
def _dpp_w64_gfx10 :
1024+
Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1025+
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1026+
let AsmString = asmName # AsmDPP;
1027+
let isAsmParserOnly = 1;
1028+
let WaveSizePredicate = isWave64;
1029+
}
1030+
}
1031+
multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1032+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
9891033
def _dpp8_gfx10 :
9901034
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
9911035
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
9921036
let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
9931037
let DecoderNamespace = "DPP8";
9941038
}
995-
996-
let WaveSizePredicate = isWave32 in {
997-
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
998-
def _sdwa_w32_gfx10 :
999-
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1000-
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1001-
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1002-
let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1003-
let isAsmParserOnly = 1;
1004-
let DecoderNamespace = "SDWA10";
1005-
}
1006-
def _dpp_w32_gfx10 :
1007-
Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1008-
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1009-
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1010-
let isAsmParserOnly = 1;
1011-
}
1012-
def _dpp8_w32_gfx10 :
1013-
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1014-
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1015-
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1016-
let isAsmParserOnly = 1;
1017-
}
1018-
} // End WaveSizePredicate = isWave32
1019-
1020-
let WaveSizePredicate = isWave64 in {
1021-
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1022-
def _sdwa_w64_gfx10 :
1023-
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1024-
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1025-
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1026-
let AsmString = asmName # Ps.AsmOperands;
1027-
let isAsmParserOnly = 1;
1028-
let DecoderNamespace = "SDWA10";
1029-
}
1030-
def _dpp_w64_gfx10 :
1031-
Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1032-
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1033-
let AsmString = asmName # AsmDPP;
1034-
let isAsmParserOnly = 1;
1035-
}
1036-
def _dpp8_w64_gfx10 :
1037-
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1038-
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1039-
let AsmString = asmName # AsmDPP8;
1040-
let isAsmParserOnly = 1;
1041-
}
1042-
} // End WaveSizePredicate = isWave64
1039+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1040+
def _dpp8_w32_gfx10 :
1041+
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1042+
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1043+
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1044+
let isAsmParserOnly = 1;
1045+
let WaveSizePredicate = isWave32;
1046+
}
1047+
foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1048+
def _dpp8_w64_gfx10 :
1049+
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1050+
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1051+
let AsmString = asmName # AsmDPP8;
1052+
let isAsmParserOnly = 1;
1053+
let WaveSizePredicate = isWave64;
1054+
}
10431055
}
10441056

10451057
//===----------------------------- VOP3Only -----------------------------===//
@@ -1060,8 +1072,19 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
10601072
}
10611073
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
10621074

1063-
multiclass Base_VOP2_Real_gfx10<bits<6> op> :
1064-
VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>;
1075+
multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1076+
VOP2be_Real_e32_gfx10<op, opName, asmName>,
1077+
VOP2be_Real_e64_gfx10<op, opName, asmName>,
1078+
VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1079+
VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1080+
VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1081+
1082+
multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1083+
VOP2_Real_e32_gfx10<op>,
1084+
VOP2_Real_e64_gfx10<op>,
1085+
VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1086+
VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1087+
VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
10651088

10661089
multiclass VOP2_Real_gfx10<bits<6> op> :
10671090
VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
@@ -1075,7 +1098,6 @@ multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
10751098
VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
10761099
VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
10771100

1078-
defm V_CNDMASK_B32 : Base_VOP2_Real_gfx10<0x001>;
10791101
defm V_XNOR_B32 : VOP2_Real_gfx10<0x01e>;
10801102
defm V_FMAC_F32 : VOP2_Real_gfx10<0x02b>;
10811103
defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10<0x02c>;
@@ -1108,6 +1130,9 @@ defm V_SUB_CO_CI_U32 :
11081130
defm V_SUBREV_CO_CI_U32 :
11091131
VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
11101132

1133+
defm V_CNDMASK_B32 :
1134+
VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1135+
11111136
// VOP3 only.
11121137
defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>;
11131138
defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>;

‎llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,26 @@ v_min_f16_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
510510
v_ldexp_f16_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
511511
// GFX10: encoding: [0xea,0x04,0x0a,0x76,0x01,0x88,0xc6,0xfa]
512512

513+
v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
514+
// W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x00,0x02,0x01,0x77,0x39,0x05]
515+
// W64-ERR: error: instruction not supported on this GPU
516+
517+
v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1
518+
// W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
519+
// W64-ERR: error: instruction not supported on this GPU
520+
521+
v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
522+
// W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x00,0x02,0x01,0x77,0x39,0x05]
523+
// W32-ERR: error: instruction not supported on this GPU
524+
525+
v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1
526+
// W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
527+
// W32-ERR: error: instruction not supported on this GPU
528+
529+
v_cndmask_b32_dpp v0, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
530+
// W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
531+
// W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
532+
513533
v_add_co_ci_u32_dpp v0, vcc_lo, v0, v0, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
514534
// W32: [0xe9,0x00,0x00,0x50,0x00,0x77,0x39,0x05]
515535
// W64-ERR: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/wave32.s

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,30 @@ v_cndmask_b32_e32 v1, v2, v3, vcc
6363
// GFX1032-ERR: error: instruction not supported on this GPU
6464
// GFX1064: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x02]
6565

66+
v_cndmask_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
67+
// GFX1032: v_cndmask_b32_sdwa v5, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
68+
// GFX1064: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
69+
70+
v_cndmask_b32_sdwa v5, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
71+
// GFX1032: v_cndmask_b32_sdwa v5, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
72+
// GFX1064-ERR: error: instruction not supported on this GPU
73+
74+
v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
75+
// GFX1032-ERR: error: instruction not supported on this GPU
76+
// GFX1064: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
77+
78+
v_cndmask_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
79+
// GFX1032: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
80+
// GFX1064: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
81+
82+
v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
83+
// GFX1032: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
84+
// GFX1064-ERR: error: instruction not supported on this GPU
85+
86+
v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
87+
// GFX1032-ERR: error: instruction not supported on this GPU
88+
// GFX1064: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
89+
6690
v_add_co_u32_e32 v2, vcc_lo, s0, v2
6791
// GFX1032-ERR: error: instruction not supported on this GPU
6892
// GFX1064-ERR: error: instruction not supported on this GPU

‎llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp16.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,14 @@
316316
# GFX10: v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
317317
0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00
318318

319+
# W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x00,0x02,0x01,0x77,0x39,0x05]
320+
# W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x00,0x02,0x01,0x77,0x39,0x05]
321+
0xe9,0x04,0x00,0x02,0x01,0x77,0x39,0x05
322+
323+
# W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
324+
# W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
325+
0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa
326+
319327
# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
320328
# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
321329
0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00

‎llvm/test/MC/Disassembler/AMDGPU/wave32.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,14 @@
3737
# GFX1064: v_cndmask_b32_e32 v1, v2, v3, vcc ;
3838
0x02,0x07,0x02,0x02
3939

40+
# GFX1032: v_cndmask_b32_sdwa v5, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
41+
# GFX1064: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
42+
0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06
43+
44+
# GFX1032: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
45+
# GFX1064: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
46+
0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00
47+
4048
# GFX1032: v_add_co_u32_e64 v2, vcc_lo, s0, v2
4149
# GFX1064: v_add_co_u32_e64 v2, vcc, s0, v2
4250
0x02,0x6a,0x0f,0xd7,0x00,0x04,0x02,0x00

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