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arsenmarsenm
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AMDGPU: Regenerate MIR test checks
Recently this started using -NEXT checks, so regenerate these to avoid extra test churn in a future change.
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+398
-363
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4 files changed

+398
-363
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll

Lines changed: 38 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -4,45 +4,51 @@
44
define float @test_atomicrmw_fadd(float addrspace(3)* %addr) {
55
; CHECK-LABEL: name: test_atomicrmw_fadd
66
; CHECK: bb.1 (%ir-block.0):
7-
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
8-
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
9-
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
10-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
11-
; CHECK: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[C]] :: (load store seq_cst (s32) on %ir.addr, addrspace 3)
12-
; CHECK: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
13-
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
14-
; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
7+
; CHECK-NEXT: liveins: $vgpr0, $sgpr30_sgpr31
8+
; CHECK-NEXT: {{ $}}
9+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
10+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
11+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
12+
; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[C]] :: (load store seq_cst (s32) on %ir.addr, addrspace 3)
13+
; CHECK-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
14+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
15+
; CHECK-NEXT: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
1516
%oldval = atomicrmw fadd float addrspace(3)* %addr, float 1.0 seq_cst
1617
ret float %oldval
1718
}
1819

1920
define float @test_atomicrmw_fsub(float addrspace(3)* %addr) {
2021
; CHECK-LABEL: name: test_atomicrmw_fsub
2122
; CHECK: bb.1 (%ir-block.0):
22-
; CHECK: successors: %bb.2(0x80000000)
23-
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
24-
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
25-
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
26-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
27-
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
28-
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32) from %ir.addr, addrspace 3)
29-
; CHECK: bb.2.atomicrmw.start:
30-
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
31-
; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI %9(s64), %bb.2, [[C1]](s64), %bb.1
32-
; CHECK: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[LOAD]](s32), %bb.1, %7(s32), %bb.2
33-
; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[PHI1]], [[C]]
34-
; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[PHI1]], [[FSUB]] :: (load store seq_cst seq_cst (s32) on %ir.2, addrspace 3)
35-
; CHECK: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
36-
; CHECK: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
37-
; CHECK: G_BRCOND [[INT1]](s1), %bb.3
38-
; CHECK: G_BR %bb.2
39-
; CHECK: bb.3.atomicrmw.end:
40-
; CHECK: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.2
41-
; CHECK: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
42-
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
43-
; CHECK: $vgpr0 = COPY [[PHI2]](s32)
44-
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
45-
; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
23+
; CHECK-NEXT: successors: %bb.2(0x80000000)
24+
; CHECK-NEXT: liveins: $vgpr0, $sgpr30_sgpr31
25+
; CHECK-NEXT: {{ $}}
26+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
27+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
28+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
29+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
30+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32) from %ir.addr, addrspace 3)
31+
; CHECK-NEXT: G_BR %bb.2
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: bb.2.atomicrmw.start:
34+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
35+
; CHECK-NEXT: {{ $}}
36+
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %9(s64), %bb.2, [[C1]](s64), %bb.1
37+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[LOAD]](s32), %bb.1, %7(s32), %bb.2
38+
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[PHI1]], [[C]]
39+
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[PHI1]], [[FSUB]] :: (load store seq_cst seq_cst (s32) on %ir.2, addrspace 3)
40+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
41+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
42+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
43+
; CHECK-NEXT: G_BR %bb.2
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: bb.3.atomicrmw.end:
46+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.2
47+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
48+
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
49+
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](s32)
50+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
51+
; CHECK-NEXT: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
4652
%oldval = atomicrmw fsub float addrspace(3)* %addr, float 1.0 seq_cst
4753
ret float %oldval
4854
}

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