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[Mips][GISel] Fix a couple issues with passing f64 in 32-bit GPRs. (llvm#69131)
MipsIncomingValueHandler::assignCustomValue should return 1 instead of 2. The return value is the number of additional ArgLocs being consumed. It's assumed that at least 1 is consumed. Correct the LocVT used for the spill when there are no registers left. It should be f64 instead of i32. This allows a workaround to be removed in the SelectionDAG path.
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-12
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3 files changed

+41
-12
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‎llvm/lib/Target/Mips/MipsCallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,7 @@ MipsIncomingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
185185

186186
markPhysRegUsed(VALo.getLocReg());
187187
markPhysRegUsed(VAHi.getLocReg());
188-
return 2;
188+
return 1;
189189
}
190190

191191
namespace {

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2948,15 +2948,15 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
29482948
Reg = State.AllocateReg(IntRegs);
29492949
LocVT = MVT::i32;
29502950
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2951-
LocVT = MVT::i32;
2952-
29532951
// Allocate int register and shadow next int register. If first
29542952
// available register is Mips::A1 or Mips::A3, shadow it too.
29552953
Reg = State.AllocateReg(IntRegs);
29562954
if (Reg == Mips::A1 || Reg == Mips::A3)
29572955
Reg = State.AllocateReg(IntRegs);
29582956

29592957
if (Reg) {
2958+
LocVT = MVT::i32;
2959+
29602960
State.addLoc(
29612961
CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
29622962
MCRegister HiReg = State.AllocateReg(IntRegs);
@@ -3723,15 +3723,6 @@ SDValue MipsTargetLowering::LowerFormalArguments(
37233723

37243724
assert(!VA.needsCustom() && "unexpected custom memory argument");
37253725

3726-
if (ABI.IsO32()) {
3727-
// We ought to be able to use LocVT directly but O32 sets it to i32
3728-
// when allocating floating point values to integer registers.
3729-
// This shouldn't influence how we load the value into registers unless
3730-
// we are targeting softfloat.
3731-
if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3732-
LocVT = VA.getValVT();
3733-
}
3734-
37353726
// Only arguments pased on the stack should make it here.
37363727
assert(VA.isMemLoc());
37373728

‎llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ define float @float_in_fpr(float %a, float %b) {
1212
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
1313
; FP32-NEXT: $f0 = COPY [[COPY1]](s32)
1414
; FP32-NEXT: RetRA implicit $f0
15+
;
1516
; FP64-LABEL: name: float_in_fpr
1617
; FP64: bb.1.entry:
1718
; FP64-NEXT: liveins: $f12, $f14
@@ -33,6 +34,7 @@ define double @double_in_fpr(double %a, double %b) {
3334
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
3435
; FP32-NEXT: $d0 = COPY [[COPY1]](s64)
3536
; FP32-NEXT: RetRA implicit $d0
37+
;
3638
; FP64-LABEL: name: double_in_fpr
3739
; FP64: bb.1.entry:
3840
; FP64-NEXT: liveins: $d12_64, $d14_64
@@ -54,6 +56,7 @@ define float @float_in_gpr(i32 %a, float %b) {
5456
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
5557
; FP32-NEXT: $f0 = COPY [[COPY1]](s32)
5658
; FP32-NEXT: RetRA implicit $f0
59+
;
5760
; FP64-LABEL: name: float_in_gpr
5861
; FP64: bb.1.entry:
5962
; FP64-NEXT: liveins: $a0, $a1
@@ -77,6 +80,7 @@ define double @double_in_gpr(i32 %a, double %b) {
7780
; FP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
7881
; FP32-NEXT: $d0 = COPY [[MV]](s64)
7982
; FP32-NEXT: RetRA implicit $d0
83+
;
8084
; FP64-LABEL: name: double_in_gpr
8185
; FP64: bb.1.entry:
8286
; FP64-NEXT: liveins: $a0, $a2, $a3
@@ -91,6 +95,36 @@ entry:
9195
ret double %b
9296
}
9397

98+
define double @two_double_in_gpr(i32 %a, double %b, double %c) {
99+
; FP32-LABEL: name: two_double_in_gpr
100+
; FP32: bb.1.entry:
101+
; FP32-NEXT: liveins: $a0, $a2, $a3
102+
; FP32-NEXT: {{ $}}
103+
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
104+
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
105+
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
106+
; FP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
107+
; FP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
108+
; FP32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0)
109+
; FP32-NEXT: $d0 = COPY [[LOAD]](s64)
110+
; FP32-NEXT: RetRA implicit $d0
111+
;
112+
; FP64-LABEL: name: two_double_in_gpr
113+
; FP64: bb.1.entry:
114+
; FP64-NEXT: liveins: $a0, $a2, $a3
115+
; FP64-NEXT: {{ $}}
116+
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
117+
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
118+
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
119+
; FP64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
120+
; FP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
121+
; FP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0)
122+
; FP64-NEXT: $d0_64 = COPY [[LOAD]](s64)
123+
; FP64-NEXT: RetRA implicit $d0_64
124+
entry:
125+
ret double %c
126+
}
127+
94128
define float @call_float_in_fpr(float %a, float %b) {
95129
; FP32-LABEL: name: call_float_in_fpr
96130
; FP32: bb.1.entry:
@@ -106,6 +140,7 @@ define float @call_float_in_fpr(float %a, float %b) {
106140
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
107141
; FP32-NEXT: $f0 = COPY [[COPY2]](s32)
108142
; FP32-NEXT: RetRA implicit $f0
143+
;
109144
; FP64-LABEL: name: call_float_in_fpr
110145
; FP64: bb.1.entry:
111146
; FP64-NEXT: liveins: $f12, $f14
@@ -140,6 +175,7 @@ define double @call_double_in_fpr(double %a, double %b) {
140175
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
141176
; FP32-NEXT: $d0 = COPY [[COPY2]](s64)
142177
; FP32-NEXT: RetRA implicit $d0
178+
;
143179
; FP64-LABEL: name: call_double_in_fpr
144180
; FP64: bb.1.entry:
145181
; FP64-NEXT: liveins: $d12_64, $d14_64
@@ -174,6 +210,7 @@ define float @call_float_in_gpr(i32 %a, float %b) {
174210
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
175211
; FP32-NEXT: $f0 = COPY [[COPY2]](s32)
176212
; FP32-NEXT: RetRA implicit $f0
213+
;
177214
; FP64-LABEL: name: call_float_in_gpr
178215
; FP64: bb.1.entry:
179216
; FP64-NEXT: liveins: $a0, $a1
@@ -213,6 +250,7 @@ define double @call_double_in_gpr(i32 %a, double %b) {
213250
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
214251
; FP32-NEXT: $d0 = COPY [[COPY3]](s64)
215252
; FP32-NEXT: RetRA implicit $d0
253+
;
216254
; FP64-LABEL: name: call_double_in_gpr
217255
; FP64: bb.1.entry:
218256
; FP64-NEXT: liveins: $a0, $a2, $a3

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