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Merge commit 'a4c461c063a2' from llvm.org/main into next
2 parents ee9fef2 + a4c461c commit 81e9d57

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-83
lines changed

3 files changed

+122
-83
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 85 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5096,14 +5096,95 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
50965096
[](ConstantSDNode *C) { return !C->isZero(); }))
50975097
return true;
50985098

5099-
// TODO: Recognize more cases here.
5099+
// TODO: Recognize more cases here. Most of the cases are also incomplete to
5100+
// some degree.
51005101
switch (Op.getOpcode()) {
5101-
default: break;
5102+
default:
5103+
break;
5104+
51025105
case ISD::OR:
5103-
if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
5104-
isKnownNeverZero(Op.getOperand(0), Depth + 1))
5106+
return isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
5107+
isKnownNeverZero(Op.getOperand(0), Depth + 1);
5108+
5109+
case ISD::VSELECT:
5110+
case ISD::SELECT:
5111+
return isKnownNeverZero(Op.getOperand(1), Depth + 1) &&
5112+
isKnownNeverZero(Op.getOperand(2), Depth + 1);
5113+
5114+
case ISD::SHL:
5115+
if (Op->getFlags().hasNoSignedWrap() || Op->getFlags().hasNoUnsignedWrap())
5116+
return isKnownNeverZero(Op.getOperand(0), Depth + 1);
5117+
5118+
// 1 << X is never zero. TODO: This can be expanded if we can bound X.
5119+
// The expression is really !Known.One[BitWidth-MaxLog2(Known):0].isZero()
5120+
if (computeKnownBits(Op.getOperand(0), Depth + 1).One[0])
5121+
return true;
5122+
break;
5123+
5124+
case ISD::UADDSAT:
5125+
case ISD::UMAX:
5126+
return isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
5127+
isKnownNeverZero(Op.getOperand(0), Depth + 1);
5128+
5129+
case ISD::UMIN:
5130+
return isKnownNeverZero(Op.getOperand(1), Depth + 1) &&
5131+
isKnownNeverZero(Op.getOperand(0), Depth + 1);
5132+
5133+
case ISD::ROTL:
5134+
case ISD::ROTR:
5135+
case ISD::BITREVERSE:
5136+
case ISD::BSWAP:
5137+
case ISD::CTPOP:
5138+
case ISD::ABS:
5139+
return isKnownNeverZero(Op.getOperand(0), Depth + 1);
5140+
5141+
case ISD::SRA:
5142+
case ISD::SRL:
5143+
if (Op->getFlags().hasExact())
5144+
return isKnownNeverZero(Op.getOperand(0), Depth + 1);
5145+
// Signed >> X is never zero. TODO: This can be expanded if we can bound X.
5146+
// The expression is really
5147+
// !Known.One[SignBit:SignBit-(BitWidth-MaxLog2(Known))].isZero()
5148+
if (computeKnownBits(Op.getOperand(0), Depth + 1).isNegative())
51055149
return true;
51065150
break;
5151+
5152+
case ISD::UDIV:
5153+
case ISD::SDIV:
5154+
// div exact can only produce a zero if the dividend is zero.
5155+
// TODO: For udiv this is also true if Op1 u<= Op0
5156+
if (Op->getFlags().hasExact())
5157+
return isKnownNeverZero(Op.getOperand(0), Depth + 1);
5158+
break;
5159+
5160+
case ISD::ADD:
5161+
if (Op->getFlags().hasNoUnsignedWrap())
5162+
if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
5163+
isKnownNeverZero(Op.getOperand(0), Depth + 1))
5164+
return true;
5165+
// TODO: There are a lot more cases we can prove for add.
5166+
break;
5167+
5168+
case ISD::SUB: {
5169+
if (isNullConstant(Op.getOperand(0)))
5170+
return isKnownNeverZero(Op.getOperand(1), Depth + 1);
5171+
5172+
std::optional<bool> ne =
5173+
KnownBits::ne(computeKnownBits(Op.getOperand(0), Depth + 1),
5174+
computeKnownBits(Op.getOperand(1), Depth + 1));
5175+
return ne && *ne;
5176+
}
5177+
5178+
case ISD::MUL:
5179+
if (Op->getFlags().hasNoSignedWrap() || Op->getFlags().hasNoUnsignedWrap())
5180+
if (isKnownNeverZero(Op.getOperand(1), Depth + 1) &&
5181+
isKnownNeverZero(Op.getOperand(0), Depth + 1))
5182+
return true;
5183+
break;
5184+
5185+
case ISD::ZERO_EXTEND:
5186+
case ISD::SIGN_EXTEND:
5187+
return isKnownNeverZero(Op.getOperand(0), Depth + 1);
51075188
}
51085189

51095190
return computeKnownBits(Op, Depth).isNonZero();

‎llvm/test/CodeGen/X86/divrem-by-select.ll

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -69,20 +69,16 @@ define <2 x i64> @udiv_identity_const_todo_getter_nonzero(<2 x i1> %c, <2 x i64>
6969
; CHECK-X64-V4: # %bb.0:
7070
; CHECK-X64-V4-NEXT: vpsllq $63, %xmm0, %xmm0
7171
; CHECK-X64-V4-NEXT: vpmovq2m %xmm0, %k1
72-
; CHECK-X64-V4-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
73-
; CHECK-X64-V4-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1}
74-
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm0, %rcx
75-
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm1, %rax
76-
; CHECK-X64-V4-NEXT: xorl %edx, %edx
77-
; CHECK-X64-V4-NEXT: divq %rcx
78-
; CHECK-X64-V4-NEXT: movq %rax, %rcx
79-
; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
80-
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
81-
; CHECK-X64-V4-NEXT: xorl %edx, %edx
82-
; CHECK-X64-V4-NEXT: divq %rsi
72+
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm1, %rdx
73+
; CHECK-X64-V4-NEXT: movabsq $-3689348814741910323, %rax # imm = 0xCCCCCCCCCCCCCCCD
74+
; CHECK-X64-V4-NEXT: mulxq %rax, %rcx, %rcx
8375
; CHECK-X64-V4-NEXT: vmovq %rcx, %xmm0
84-
; CHECK-X64-V4-NEXT: vmovq %rax, %xmm1
85-
; CHECK-X64-V4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
76+
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rdx
77+
; CHECK-X64-V4-NEXT: mulxq %rax, %rax, %rax
78+
; CHECK-X64-V4-NEXT: vmovq %rax, %xmm2
79+
; CHECK-X64-V4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
80+
; CHECK-X64-V4-NEXT: vpsrlq $3, %xmm0, %xmm1 {%k1}
81+
; CHECK-X64-V4-NEXT: vmovdqa %xmm1, %xmm0
8682
; CHECK-X64-V4-NEXT: retq
8783

8884
;; Fails at the moment because `10` is even so there is no common
@@ -118,23 +114,23 @@ define <2 x i64> @udiv_indentity_non_zero(<2 x i1> %c, <2 x i64> %x, <2 x i64> %
118114
;
119115
; CHECK-X64-V4-LABEL: udiv_indentity_non_zero:
120116
; CHECK-X64-V4: # %bb.0:
121-
; CHECK-X64-V4-NEXT: vpsllq $63, %xmm0, %xmm0
122-
; CHECK-X64-V4-NEXT: vpmovq2m %xmm0, %k1
123-
; CHECK-X64-V4-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
124-
; CHECK-X64-V4-NEXT: vpbroadcastq {{.*#+}} xmm3 = [1,1]
125-
; CHECK-X64-V4-NEXT: vpsubq %xmm0, %xmm2, %xmm3 {%k1}
126-
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm3, %rcx
117+
; CHECK-X64-V4-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
118+
; CHECK-X64-V4-NEXT: vpsubq %xmm3, %xmm2, %xmm2
119+
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm2, %rcx
127120
; CHECK-X64-V4-NEXT: vpextrq $1, %xmm1, %rax
128121
; CHECK-X64-V4-NEXT: xorl %edx, %edx
129122
; CHECK-X64-V4-NEXT: divq %rcx
130123
; CHECK-X64-V4-NEXT: movq %rax, %rcx
131-
; CHECK-X64-V4-NEXT: vmovq %xmm3, %rsi
124+
; CHECK-X64-V4-NEXT: vmovq %xmm2, %rsi
132125
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
133126
; CHECK-X64-V4-NEXT: xorl %edx, %edx
134127
; CHECK-X64-V4-NEXT: divq %rsi
128+
; CHECK-X64-V4-NEXT: vpsllq $63, %xmm0, %xmm0
129+
; CHECK-X64-V4-NEXT: vpmovq2m %xmm0, %k1
135130
; CHECK-X64-V4-NEXT: vmovq %rcx, %xmm0
136-
; CHECK-X64-V4-NEXT: vmovq %rax, %xmm1
137-
; CHECK-X64-V4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
131+
; CHECK-X64-V4-NEXT: vmovq %rax, %xmm2
132+
; CHECK-X64-V4-NEXT: vpunpcklqdq {{.*#+}} xmm1 {%k1} = xmm2[0],xmm0[0]
133+
; CHECK-X64-V4-NEXT: vmovdqa %xmm1, %xmm0
138134
; CHECK-X64-V4-NEXT: retq
139135
%non_zero = add nsw nuw <2 x i64> %y, <i64 1, i64 1>
140136
%d = select <2 x i1> %c, <2 x i64> %non_zero, <2 x i64> <i64 1, i64 1>

‎llvm/test/CodeGen/X86/known-never-zero.ll

Lines changed: 19 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -49,9 +49,7 @@ define i32 @select_known_nonzero(i1 %c, i32 %x) {
4949
; CHECK-NEXT: testb $1, %dil
5050
; CHECK-NEXT: movl $122, %eax
5151
; CHECK-NEXT: cmovnel %esi, %eax
52-
; CHECK-NEXT: bsfl %eax, %ecx
53-
; CHECK-NEXT: movl $32, %eax
54-
; CHECK-NEXT: cmovnel %ecx, %eax
52+
; CHECK-NEXT: rep bsfl %eax, %eax
5553
; CHECK-NEXT: retq
5654
%y = or i32 %x, 1
5755
%z = select i1 %c, i32 %y, i32 122
@@ -87,9 +85,7 @@ define i32 @shl_known_nonzero_1s_bit_set(i32 %x) {
8785
; CHECK-NEXT: movl $123, %eax
8886
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
8987
; CHECK-NEXT: shll %cl, %eax
90-
; CHECK-NEXT: bsfl %eax, %ecx
91-
; CHECK-NEXT: movl $32, %eax
92-
; CHECK-NEXT: cmovnel %ecx, %eax
88+
; CHECK-NEXT: rep bsfl %eax, %eax
9389
; CHECK-NEXT: retq
9490
%z = shl i32 123, %x
9591
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
@@ -103,9 +99,7 @@ define i32 @shl_known_nonzero_nsw(i32 %x, i32 %yy) {
10399
; CHECK-NEXT: orl $256, %esi # imm = 0x100
104100
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
105101
; CHECK-NEXT: shll %cl, %esi
106-
; CHECK-NEXT: bsfl %esi, %ecx
107-
; CHECK-NEXT: movl $32, %eax
108-
; CHECK-NEXT: cmovnel %ecx, %eax
102+
; CHECK-NEXT: rep bsfl %esi, %eax
109103
; CHECK-NEXT: retq
110104
%y = or i32 %yy, 256
111105
%z = shl nsw i32 %y, %x
@@ -120,9 +114,7 @@ define i32 @shl_known_nonzero_nuw(i32 %x, i32 %yy) {
120114
; CHECK-NEXT: orl $256, %esi # imm = 0x100
121115
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
122116
; CHECK-NEXT: shll %cl, %esi
123-
; CHECK-NEXT: bsfl %esi, %ecx
124-
; CHECK-NEXT: movl $32, %eax
125-
; CHECK-NEXT: cmovnel %ecx, %eax
117+
; CHECK-NEXT: rep bsfl %esi, %eax
126118
; CHECK-NEXT: retq
127119
%y = or i32 %yy, 256
128120
%z = shl nuw i32 %y, %x
@@ -155,9 +147,7 @@ define i32 @uaddsat_known_nonzero(i32 %x) {
155147
; CHECK-NEXT: incl %edi
156148
; CHECK-NEXT: movl $-1, %eax
157149
; CHECK-NEXT: cmovnel %edi, %eax
158-
; CHECK-NEXT: bsfl %eax, %ecx
159-
; CHECK-NEXT: movl $32, %eax
160-
; CHECK-NEXT: cmovnel %ecx, %eax
150+
; CHECK-NEXT: rep bsfl %eax, %eax
161151
; CHECK-NEXT: retq
162152
%z = call i32 @llvm.uadd.sat.i32(i32 %x, i32 1)
163153
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
@@ -192,9 +182,7 @@ define i32 @umax_known_nonzero(i32 %x, i32 %y) {
192182
; CHECK-NEXT: shll %cl, %eax
193183
; CHECK-NEXT: cmpl %eax, %edi
194184
; CHECK-NEXT: cmoval %edi, %eax
195-
; CHECK-NEXT: bsfl %eax, %ecx
196-
; CHECK-NEXT: movl $32, %eax
197-
; CHECK-NEXT: cmovnel %ecx, %eax
185+
; CHECK-NEXT: rep bsfl %eax, %eax
198186
; CHECK-NEXT: retq
199187
%yy = shl nuw i32 4, %y
200188
%z = call i32 @llvm.umax.i32(i32 %x, i32 %yy)
@@ -230,9 +218,7 @@ define i32 @umin_known_nonzero(i32 %xx, i32 %yy) {
230218
; CHECK-NEXT: addl $4, %esi
231219
; CHECK-NEXT: cmpl %esi, %eax
232220
; CHECK-NEXT: cmovbl %eax, %esi
233-
; CHECK-NEXT: bsfl %esi, %ecx
234-
; CHECK-NEXT: movl $32, %eax
235-
; CHECK-NEXT: cmovnel %ecx, %eax
221+
; CHECK-NEXT: rep bsfl %esi, %eax
236222
; CHECK-NEXT: retq
237223
%x = shl nuw i32 4, %xx
238224
%y = add nuw nsw i32 %yy, 4
@@ -313,9 +299,7 @@ define i32 @rotr_with_fshr_known_nonzero(i32 %xx, i32 %y) {
313299
; CHECK-NEXT: orl $256, %edi # imm = 0x100
314300
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
315301
; CHECK-NEXT: rorl %cl, %edi
316-
; CHECK-NEXT: bsfl %edi, %ecx
317-
; CHECK-NEXT: movl $32, %eax
318-
; CHECK-NEXT: cmovnel %ecx, %eax
302+
; CHECK-NEXT: rep bsfl %edi, %eax
319303
; CHECK-NEXT: retq
320304
%x = or i32 %xx, 256
321305
%z = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %y)
@@ -395,9 +379,7 @@ define i32 @rotl_with_fshl_known_nonzero(i32 %xx, i32 %y) {
395379
; CHECK-NEXT: orl $256, %edi # imm = 0x100
396380
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
397381
; CHECK-NEXT: roll %cl, %edi
398-
; CHECK-NEXT: bsfl %edi, %ecx
399-
; CHECK-NEXT: movl $32, %eax
400-
; CHECK-NEXT: cmovnel %ecx, %eax
382+
; CHECK-NEXT: rep bsfl %edi, %eax
401383
; CHECK-NEXT: retq
402384
%x = or i32 %xx, 256
403385
%z = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %y)
@@ -445,9 +427,7 @@ define i32 @sra_known_nonzero_exact(i32 %x, i32 %yy) {
445427
; CHECK-NEXT: orl $256, %esi # imm = 0x100
446428
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
447429
; CHECK-NEXT: sarl %cl, %esi
448-
; CHECK-NEXT: bsfl %esi, %ecx
449-
; CHECK-NEXT: movl $32, %eax
450-
; CHECK-NEXT: cmovnel %ecx, %eax
430+
; CHECK-NEXT: rep bsfl %esi, %eax
451431
; CHECK-NEXT: retq
452432
%y = or i32 %yy, 256
453433
%z = ashr exact i32 %y, %x
@@ -481,9 +461,7 @@ define i32 @srl_known_nonzero_sign_bit_set(i32 %x) {
481461
; CHECK-NEXT: movl $-2147360405, %eax # imm = 0x8001E16B
482462
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
483463
; CHECK-NEXT: shrl %cl, %eax
484-
; CHECK-NEXT: bsfl %eax, %ecx
485-
; CHECK-NEXT: movl $32, %eax
486-
; CHECK-NEXT: cmovnel %ecx, %eax
464+
; CHECK-NEXT: rep bsfl %eax, %eax
487465
; CHECK-NEXT: retq
488466
%z = lshr i32 2147606891, %x
489467
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
@@ -497,9 +475,7 @@ define i32 @srl_known_nonzero_exact(i32 %x, i32 %yy) {
497475
; CHECK-NEXT: orl $256, %esi # imm = 0x100
498476
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
499477
; CHECK-NEXT: shrl %cl, %esi
500-
; CHECK-NEXT: bsfl %esi, %ecx
501-
; CHECK-NEXT: movl $32, %eax
502-
; CHECK-NEXT: cmovnel %ecx, %eax
478+
; CHECK-NEXT: rep bsfl %esi, %eax
503479
; CHECK-NEXT: retq
504480
%y = or i32 %yy, 256
505481
%z = lshr exact i32 %y, %x
@@ -533,9 +509,7 @@ define i32 @udiv_known_nonzero(i32 %xx, i32 %y) {
533509
; CHECK-NEXT: orl $64, %eax
534510
; CHECK-NEXT: xorl %edx, %edx
535511
; CHECK-NEXT: divl %esi
536-
; CHECK-NEXT: bsfl %eax, %ecx
537-
; CHECK-NEXT: movl $32, %eax
538-
; CHECK-NEXT: cmovnel %ecx, %eax
512+
; CHECK-NEXT: rep bsfl %eax, %eax
539513
; CHECK-NEXT: retq
540514
%x = or i32 %xx, 64
541515
%z = udiv exact i32 %x, %y
@@ -569,9 +543,7 @@ define i32 @sdiv_known_nonzero(i32 %xx, i32 %y) {
569543
; CHECK-NEXT: orl $64, %eax
570544
; CHECK-NEXT: cltd
571545
; CHECK-NEXT: idivl %esi
572-
; CHECK-NEXT: bsfl %eax, %ecx
573-
; CHECK-NEXT: movl $32, %eax
574-
; CHECK-NEXT: cmovnel %ecx, %eax
546+
; CHECK-NEXT: rep bsfl %eax, %eax
575547
; CHECK-NEXT: retq
576548
%x = or i32 %xx, 64
577549
%z = sdiv exact i32 %x, %y
@@ -603,9 +575,7 @@ define i32 @add_known_nonzero(i32 %xx, i32 %y) {
603575
; CHECK: # %bb.0:
604576
; CHECK-NEXT: orl $1, %edi
605577
; CHECK-NEXT: addl %esi, %edi
606-
; CHECK-NEXT: bsfl %edi, %ecx
607-
; CHECK-NEXT: movl $32, %eax
608-
; CHECK-NEXT: cmovnel %ecx, %eax
578+
; CHECK-NEXT: rep bsfl %edi, %eax
609579
; CHECK-NEXT: retq
610580
%x = or i32 %xx, 1
611581
%z = add nuw i32 %x, %y
@@ -639,9 +609,7 @@ define i32 @sub_known_nonzero_neg_case(i32 %xx) {
639609
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
640610
; CHECK-NEXT: shll %cl, %eax
641611
; CHECK-NEXT: negl %eax
642-
; CHECK-NEXT: bsfl %eax, %ecx
643-
; CHECK-NEXT: movl $32, %eax
644-
; CHECK-NEXT: cmovnel %ecx, %eax
612+
; CHECK-NEXT: rep bsfl %eax, %eax
645613
; CHECK-NEXT: retq
646614
%x = shl nuw nsw i32 256, %xx
647615
%z = sub i32 0, %x
@@ -656,9 +624,7 @@ define i32 @sub_known_nonzero_ne_case(i32 %xx, i32 %yy) {
656624
; CHECK-NEXT: orl $64, %eax
657625
; CHECK-NEXT: andl $-65, %edi
658626
; CHECK-NEXT: subl %eax, %edi
659-
; CHECK-NEXT: bsfl %edi, %ecx
660-
; CHECK-NEXT: movl $32, %eax
661-
; CHECK-NEXT: cmovnel %ecx, %eax
627+
; CHECK-NEXT: rep bsfl %edi, %eax
662628
; CHECK-NEXT: retq
663629
%x = or i32 %xx, 64
664630
%y = and i32 %xx, -65
@@ -819,9 +785,7 @@ define i32 @zext_known_nonzero(i16 %xx) {
819785
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
820786
; CHECK-NEXT: shll %cl, %eax
821787
; CHECK-NEXT: movzwl %ax, %eax
822-
; CHECK-NEXT: bsfl %eax, %ecx
823-
; CHECK-NEXT: movl $32, %eax
824-
; CHECK-NEXT: cmovnel %ecx, %eax
788+
; CHECK-NEXT: rep bsfl %eax, %eax
825789
; CHECK-NEXT: retq
826790
%x = shl nuw nsw i16 256, %xx
827791
%z = zext i16 %x to i32
@@ -854,9 +818,7 @@ define i32 @sext_known_nonzero(i16 %xx) {
854818
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
855819
; CHECK-NEXT: shll %cl, %eax
856820
; CHECK-NEXT: cwtl
857-
; CHECK-NEXT: bsfl %eax, %ecx
858-
; CHECK-NEXT: movl $32, %eax
859-
; CHECK-NEXT: cmovnel %ecx, %eax
821+
; CHECK-NEXT: rep bsfl %eax, %eax
860822
; CHECK-NEXT: retq
861823
%x = shl nuw nsw i16 256, %xx
862824
%z = sext i16 %x to i32

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