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Cameron McInally
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[NFCI][SVE] Move fixed length i32/i64 SDIV tests
Move fixed length SDIV tests from sve-fixed-length-int-arith.ll to sve-fixed-length-int-div.ll. The former uses CHECK lines that verify legalization decisions. That's overkill for the i8/i16 SDIV tests, since they have a tricky legalization.
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‎llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

Lines changed: 0 additions & 164 deletions
Original file line numberDiff line numberDiff line change
@@ -419,170 +419,6 @@ define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
419419
; VBYTES because the add tests already validate the legalisation code paths.
420420
;
421421

422-
;
423-
; SDIV
424-
;
425-
426-
; Vector v2i32 sdiv are not legal for NEON so use SVE when available.
427-
define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
428-
; CHECK-LABEL: sdiv_v2i32:
429-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),2)]]
430-
; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
431-
; CHECK: ret
432-
%res = sdiv <2 x i32> %op1, %op2
433-
ret <2 x i32> %res
434-
}
435-
436-
; Vector v4i32 sdiv are not legal for NEON so use SVE when available.
437-
define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
438-
; CHECK-LABEL: sdiv_v4i32:
439-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),4)]]
440-
; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
441-
; CHECK: ret
442-
%res = sdiv <4 x i32> %op1, %op2
443-
ret <4 x i32> %res
444-
}
445-
446-
define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
447-
; CHECK-LABEL: sdiv_v8i32:
448-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
449-
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
450-
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
451-
; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
452-
; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
453-
; CHECK: ret
454-
%op1 = load <8 x i32>, <8 x i32>* %a
455-
%op2 = load <8 x i32>, <8 x i32>* %b
456-
%res = sdiv <8 x i32> %op1, %op2
457-
store <8 x i32> %res, <8 x i32>* %a
458-
ret void
459-
}
460-
461-
define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
462-
; CHECK-LABEL: sdiv_v16i32:
463-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
464-
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
465-
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
466-
; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
467-
; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
468-
; CHECK: ret
469-
%op1 = load <16 x i32>, <16 x i32>* %a
470-
%op2 = load <16 x i32>, <16 x i32>* %b
471-
%res = sdiv <16 x i32> %op1, %op2
472-
store <16 x i32> %res, <16 x i32>* %a
473-
ret void
474-
}
475-
476-
define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
477-
; CHECK-LABEL: sdiv_v32i32:
478-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
479-
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
480-
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
481-
; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
482-
; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
483-
; CHECK: ret
484-
%op1 = load <32 x i32>, <32 x i32>* %a
485-
%op2 = load <32 x i32>, <32 x i32>* %b
486-
%res = sdiv <32 x i32> %op1, %op2
487-
store <32 x i32> %res, <32 x i32>* %a
488-
ret void
489-
}
490-
491-
define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
492-
; CHECK-LABEL: sdiv_v64i32:
493-
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
494-
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
495-
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
496-
; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
497-
; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
498-
; CHECK: ret
499-
%op1 = load <64 x i32>, <64 x i32>* %a
500-
%op2 = load <64 x i32>, <64 x i32>* %b
501-
%res = sdiv <64 x i32> %op1, %op2
502-
store <64 x i32> %res, <64 x i32>* %a
503-
ret void
504-
}
505-
506-
; Vector i64 sdiv are not legal for NEON so use SVE when available.
507-
define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
508-
; CHECK-LABEL: sdiv_v1i64:
509-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
510-
; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
511-
; CHECK: ret
512-
%res = sdiv <1 x i64> %op1, %op2
513-
ret <1 x i64> %res
514-
}
515-
516-
; Vector i64 sdiv are not legal for NEON so use SVE when available.
517-
define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
518-
; CHECK-LABEL: sdiv_v2i64:
519-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
520-
; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
521-
; CHECK: ret
522-
%res = sdiv <2 x i64> %op1, %op2
523-
ret <2 x i64> %res
524-
}
525-
526-
define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
527-
; CHECK-LABEL: sdiv_v4i64:
528-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
529-
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
530-
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
531-
; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
532-
; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
533-
; CHECK: ret
534-
%op1 = load <4 x i64>, <4 x i64>* %a
535-
%op2 = load <4 x i64>, <4 x i64>* %b
536-
%res = sdiv <4 x i64> %op1, %op2
537-
store <4 x i64> %res, <4 x i64>* %a
538-
ret void
539-
}
540-
541-
define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
542-
; CHECK-LABEL: sdiv_v8i64:
543-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
544-
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
545-
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
546-
; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
547-
; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
548-
; CHECK: ret
549-
%op1 = load <8 x i64>, <8 x i64>* %a
550-
%op2 = load <8 x i64>, <8 x i64>* %b
551-
%res = sdiv <8 x i64> %op1, %op2
552-
store <8 x i64> %res, <8 x i64>* %a
553-
ret void
554-
}
555-
556-
define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
557-
; CHECK-LABEL: sdiv_v16i64:
558-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
559-
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
560-
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
561-
; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
562-
; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
563-
; CHECK: ret
564-
%op1 = load <16 x i64>, <16 x i64>* %a
565-
%op2 = load <16 x i64>, <16 x i64>* %b
566-
%res = sdiv <16 x i64> %op1, %op2
567-
store <16 x i64> %res, <16 x i64>* %a
568-
ret void
569-
}
570-
571-
define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
572-
; CHECK-LABEL: sdiv_v32i64:
573-
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
574-
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
575-
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
576-
; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
577-
; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
578-
; CHECK: ret
579-
%op1 = load <32 x i64>, <32 x i64>* %a
580-
%op2 = load <32 x i64>, <32 x i64>* %b
581-
%res = sdiv <32 x i64> %op1, %op2
582-
store <32 x i64> %res, <32 x i64>* %a
583-
ret void
584-
}
585-
586422
;
587423
; MUL
588424
;

‎llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -334,4 +334,164 @@ define void @sdiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
334334
ret void
335335
}
336336

337+
; Vector v2i32 sdiv are not legal for NEON so use SVE when available.
338+
define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
339+
; CHECK-LABEL: sdiv_v2i32:
340+
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),2)]]
341+
; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
342+
; CHECK: ret
343+
%res = sdiv <2 x i32> %op1, %op2
344+
ret <2 x i32> %res
345+
}
346+
347+
; Vector v4i32 sdiv are not legal for NEON so use SVE when available.
348+
define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
349+
; CHECK-LABEL: sdiv_v4i32:
350+
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),4)]]
351+
; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
352+
; CHECK: ret
353+
%res = sdiv <4 x i32> %op1, %op2
354+
ret <4 x i32> %res
355+
}
356+
357+
define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
358+
; CHECK-LABEL: sdiv_v8i32:
359+
; VBITS_GE_256: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
360+
; VBITS_GE_256-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
361+
; VBITS_GE_256-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
362+
; VBITS_GE_256-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
363+
; VBITS_GE_256-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
364+
; VBITS_GE_256-NEXT: ret
365+
%op1 = load <8 x i32>, <8 x i32>* %a
366+
%op2 = load <8 x i32>, <8 x i32>* %b
367+
%res = sdiv <8 x i32> %op1, %op2
368+
store <8 x i32> %res, <8 x i32>* %a
369+
ret void
370+
}
371+
372+
define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
373+
; CHECK-LABEL: sdiv_v16i32:
374+
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
375+
; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
376+
; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
377+
; VBITS_GE_512-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
378+
; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
379+
; VBITS_GE_512-NEXT: ret
380+
%op1 = load <16 x i32>, <16 x i32>* %a
381+
%op2 = load <16 x i32>, <16 x i32>* %b
382+
%res = sdiv <16 x i32> %op1, %op2
383+
store <16 x i32> %res, <16 x i32>* %a
384+
ret void
385+
}
386+
387+
define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
388+
; CHECK-LABEL: sdiv_v32i32:
389+
; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
390+
; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
391+
; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
392+
; VBITS_GE_1024-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
393+
; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
394+
; VBITS_GE_1024-NEXT: ret
395+
%op1 = load <32 x i32>, <32 x i32>* %a
396+
%op2 = load <32 x i32>, <32 x i32>* %b
397+
%res = sdiv <32 x i32> %op1, %op2
398+
store <32 x i32> %res, <32 x i32>* %a
399+
ret void
400+
}
401+
402+
define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
403+
; CHECK-LABEL: sdiv_v64i32:
404+
; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
405+
; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
406+
; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
407+
; VBITS_GE_2048-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
408+
; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
409+
; VBITS_GE_2048-NEXT: ret
410+
%op1 = load <64 x i32>, <64 x i32>* %a
411+
%op2 = load <64 x i32>, <64 x i32>* %b
412+
%res = sdiv <64 x i32> %op1, %op2
413+
store <64 x i32> %res, <64 x i32>* %a
414+
ret void
415+
}
416+
417+
; Vector i64 sdiv are not legal for NEON so use SVE when available.
418+
define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
419+
; CHECK-LABEL: sdiv_v1i64:
420+
; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
421+
; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
422+
; CHECK: ret
423+
%res = sdiv <1 x i64> %op1, %op2
424+
ret <1 x i64> %res
425+
}
426+
427+
; Vector i64 sdiv are not legal for NEON so use SVE when available.
428+
define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
429+
; CHECK-LABEL: sdiv_v2i64:
430+
; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
431+
; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
432+
; CHECK: ret
433+
%res = sdiv <2 x i64> %op1, %op2
434+
ret <2 x i64> %res
435+
}
436+
437+
define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
438+
; CHECK-LABEL: sdiv_v4i64:
439+
; VBITS_GE_256: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
440+
; VBITS_GE_256-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
441+
; VBITS_GE_256-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
442+
; VBITS_GE_256-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
443+
; VBITS_GE_256-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
444+
; VBITS_GE_256-NEXT: ret
445+
%op1 = load <4 x i64>, <4 x i64>* %a
446+
%op2 = load <4 x i64>, <4 x i64>* %b
447+
%res = sdiv <4 x i64> %op1, %op2
448+
store <4 x i64> %res, <4 x i64>* %a
449+
ret void
450+
}
451+
452+
define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
453+
; CHECK-LABEL: sdiv_v8i64:
454+
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
455+
; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
456+
; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
457+
; VBITS_GE_512-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
458+
; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
459+
; VBITS_GE_512-NEXT: ret
460+
%op1 = load <8 x i64>, <8 x i64>* %a
461+
%op2 = load <8 x i64>, <8 x i64>* %b
462+
%res = sdiv <8 x i64> %op1, %op2
463+
store <8 x i64> %res, <8 x i64>* %a
464+
ret void
465+
}
466+
467+
define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
468+
; CHECK-LABEL: sdiv_v16i64:
469+
; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
470+
; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
471+
; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
472+
; VBITS_GE_1024-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
473+
; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
474+
; VBITS_GE_1024-NEXT: ret
475+
%op1 = load <16 x i64>, <16 x i64>* %a
476+
%op2 = load <16 x i64>, <16 x i64>* %b
477+
%res = sdiv <16 x i64> %op1, %op2
478+
store <16 x i64> %res, <16 x i64>* %a
479+
ret void
480+
}
481+
482+
define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v32i64:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
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; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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; VBITS_GE_2048-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
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; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
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; VBITS_GE_2048-NEXT: ret
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%op1 = load <32 x i64>, <32 x i64>* %a
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%op2 = load <32 x i64>, <32 x i64>* %b
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%res = sdiv <32 x i64> %op1, %op2
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store <32 x i64> %res, <32 x i64>* %a
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ret void
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}
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attributes #0 = { "target-features"="+sve" }

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