Skip to content

Commit 83b8f8d

Browse files
frasercrmckfrasercrmck
committed
[RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max)
This patch adds support for both scalable- and fixed-length vector code lowering of the llvm.minnum and llvm.maxnum intrinsics to the equivalent RVV instructions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D101035
1 parent f3e6f85 commit 83b8f8d

File tree

8 files changed

+1339
-0
lines changed

8 files changed

+1339
-0
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -555,6 +555,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
555555
for (auto CC : VFPCCToExpand)
556556
setCondCodeAction(CC, VT, Expand);
557557

558+
setOperationAction(ISD::FMINNUM, VT, Legal);
559+
setOperationAction(ISD::FMAXNUM, VT, Legal);
560+
558561
setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
559562
setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
560563
setOperationAction(ISD::FCOPYSIGN, VT, Legal);
@@ -729,6 +732,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
729732
setOperationAction(ISD::FCOPYSIGN, VT, Custom);
730733
setOperationAction(ISD::FSQRT, VT, Custom);
731734
setOperationAction(ISD::FMA, VT, Custom);
735+
setOperationAction(ISD::FMINNUM, VT, Custom);
736+
setOperationAction(ISD::FMAXNUM, VT, Custom);
732737

733738
setOperationAction(ISD::FP_ROUND, VT, Custom);
734739
setOperationAction(ISD::FP_EXTEND, VT, Custom);
@@ -2205,6 +2210,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
22052210
return lowerToScalableOp(Op, DAG, RISCVISD::UMIN_VL);
22062211
case ISD::UMAX:
22072212
return lowerToScalableOp(Op, DAG, RISCVISD::UMAX_VL);
2213+
case ISD::FMINNUM:
2214+
return lowerToScalableOp(Op, DAG, RISCVISD::FMINNUM_VL);
2215+
case ISD::FMAXNUM:
2216+
return lowerToScalableOp(Op, DAG, RISCVISD::FMAXNUM_VL);
22082217
case ISD::ABS:
22092218
return lowerABS(Op, DAG);
22102219
case ISD::VSELECT:
@@ -7457,6 +7466,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
74577466
NODE_NAME_CASE(SMAX_VL)
74587467
NODE_NAME_CASE(UMIN_VL)
74597468
NODE_NAME_CASE(UMAX_VL)
7469+
NODE_NAME_CASE(FMINNUM_VL)
7470+
NODE_NAME_CASE(FMAXNUM_VL)
74607471
NODE_NAME_CASE(MULHS_VL)
74617472
NODE_NAME_CASE(MULHU_VL)
74627473
NODE_NAME_CASE(FP_TO_SINT_VL)

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,8 @@ enum NodeType : unsigned {
194194
SMAX_VL,
195195
UMIN_VL,
196196
UMAX_VL,
197+
FMINNUM_VL,
198+
FMAXNUM_VL,
197199
MULHS_VL,
198200
MULHU_VL,
199201
FP_TO_SINT_VL,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -635,6 +635,10 @@ foreach vti = AllFloatVectors in {
635635
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.SEW)>;
636636
}
637637

638+
// 14.11. Vector Floating-Point MIN/MAX Instructions
639+
defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN">;
640+
defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX">;
641+
638642
// 14.13. Vector Floating-Point Compare Instructions
639643
defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
640644
defm : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,8 @@ def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>;
9797
def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>;
9898
def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>;
9999
def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>;
100+
def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>;
101+
def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>;
100102

101103
def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
102104
SDTCisSameAs<0, 2>,
@@ -856,6 +858,10 @@ foreach vti = AllFloatVectors in {
856858
GPR:$vl, vti.SEW)>;
857859
}
858860

861+
// 14.11. Vector Floating-Point MIN/MAX Instructions
862+
defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">;
863+
defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">;
864+
859865
// 14.13. Vector Floating-Point Compare Instructions
860866
defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
861867
defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll

Lines changed: 293 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,293 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
3+
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
5+
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
6+
7+
declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
8+
9+
define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
10+
; CHECK-LABEL: vfmax_v2f16_vv:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
13+
; CHECK-NEXT: vfmax.vv v8, v8, v9
14+
; CHECK-NEXT: ret
15+
%v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
16+
ret <2 x half> %v
17+
}
18+
19+
define <2 x half> @vfmax_v2f16_vf(<2 x half> %a, half %b) {
20+
; CHECK-LABEL: vfmax_v2f16_vf:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
23+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
24+
; CHECK-NEXT: ret
25+
%head = insertelement <2 x half> undef, half %b, i32 0
26+
%splat = shufflevector <2 x half> %head, <2 x half> undef, <2 x i32> zeroinitializer
27+
%v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %splat)
28+
ret <2 x half> %v
29+
}
30+
31+
declare <4 x half> @llvm.maxnum.v4f16(<4 x half>, <4 x half>)
32+
33+
define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
34+
; CHECK-LABEL: vfmax_v4f16_vv:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
37+
; CHECK-NEXT: vfmax.vv v8, v8, v9
38+
; CHECK-NEXT: ret
39+
%v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %b)
40+
ret <4 x half> %v
41+
}
42+
43+
define <4 x half> @vfmax_v4f16_vf(<4 x half> %a, half %b) {
44+
; CHECK-LABEL: vfmax_v4f16_vf:
45+
; CHECK: # %bb.0:
46+
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
47+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
48+
; CHECK-NEXT: ret
49+
%head = insertelement <4 x half> undef, half %b, i32 0
50+
%splat = shufflevector <4 x half> %head, <4 x half> undef, <4 x i32> zeroinitializer
51+
%v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %splat)
52+
ret <4 x half> %v
53+
}
54+
55+
declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>)
56+
57+
define <8 x half> @vfmax_v8f16_vv(<8 x half> %a, <8 x half> %b) {
58+
; CHECK-LABEL: vfmax_v8f16_vv:
59+
; CHECK: # %bb.0:
60+
; CHECK-NEXT: vsetivli a0, 8, e16,m1,ta,mu
61+
; CHECK-NEXT: vfmax.vv v8, v8, v9
62+
; CHECK-NEXT: ret
63+
%v = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %b)
64+
ret <8 x half> %v
65+
}
66+
67+
define <8 x half> @vfmax_v8f16_vf(<8 x half> %a, half %b) {
68+
; CHECK-LABEL: vfmax_v8f16_vf:
69+
; CHECK: # %bb.0:
70+
; CHECK-NEXT: vsetivli a0, 8, e16,m1,ta,mu
71+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
72+
; CHECK-NEXT: ret
73+
%head = insertelement <8 x half> undef, half %b, i32 0
74+
%splat = shufflevector <8 x half> %head, <8 x half> undef, <8 x i32> zeroinitializer
75+
%v = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %splat)
76+
ret <8 x half> %v
77+
}
78+
79+
declare <16 x half> @llvm.maxnum.v16f16(<16 x half>, <16 x half>)
80+
81+
define <16 x half> @vfmax_v16f16_vv(<16 x half> %a, <16 x half> %b) {
82+
; CHECK-LABEL: vfmax_v16f16_vv:
83+
; CHECK: # %bb.0:
84+
; CHECK-NEXT: vsetivli a0, 16, e16,m2,ta,mu
85+
; CHECK-NEXT: vfmax.vv v8, v8, v10
86+
; CHECK-NEXT: ret
87+
%v = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %a, <16 x half> %b)
88+
ret <16 x half> %v
89+
}
90+
91+
define <16 x half> @vfmax_v16f16_vf(<16 x half> %a, half %b) {
92+
; CHECK-LABEL: vfmax_v16f16_vf:
93+
; CHECK: # %bb.0:
94+
; CHECK-NEXT: vsetivli a0, 16, e16,m2,ta,mu
95+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
96+
; CHECK-NEXT: ret
97+
%head = insertelement <16 x half> undef, half %b, i32 0
98+
%splat = shufflevector <16 x half> %head, <16 x half> undef, <16 x i32> zeroinitializer
99+
%v = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %a, <16 x half> %splat)
100+
ret <16 x half> %v
101+
}
102+
103+
declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
104+
105+
define <2 x float> @vfmax_v2f32_vv(<2 x float> %a, <2 x float> %b) {
106+
; CHECK-LABEL: vfmax_v2f32_vv:
107+
; CHECK: # %bb.0:
108+
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
109+
; CHECK-NEXT: vfmax.vv v8, v8, v9
110+
; CHECK-NEXT: ret
111+
%v = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
112+
ret <2 x float> %v
113+
}
114+
115+
define <2 x float> @vfmax_v2f32_vf(<2 x float> %a, float %b) {
116+
; CHECK-LABEL: vfmax_v2f32_vf:
117+
; CHECK: # %bb.0:
118+
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
119+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
120+
; CHECK-NEXT: ret
121+
%head = insertelement <2 x float> undef, float %b, i32 0
122+
%splat = shufflevector <2 x float> %head, <2 x float> undef, <2 x i32> zeroinitializer
123+
%v = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %splat)
124+
ret <2 x float> %v
125+
}
126+
127+
declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
128+
129+
define <4 x float> @vfmax_v4f32_vv(<4 x float> %a, <4 x float> %b) {
130+
; CHECK-LABEL: vfmax_v4f32_vv:
131+
; CHECK: # %bb.0:
132+
; CHECK-NEXT: vsetivli a0, 4, e32,m1,ta,mu
133+
; CHECK-NEXT: vfmax.vv v8, v8, v9
134+
; CHECK-NEXT: ret
135+
%v = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
136+
ret <4 x float> %v
137+
}
138+
139+
define <4 x float> @vfmax_v4f32_vf(<4 x float> %a, float %b) {
140+
; CHECK-LABEL: vfmax_v4f32_vf:
141+
; CHECK: # %bb.0:
142+
; CHECK-NEXT: vsetivli a0, 4, e32,m1,ta,mu
143+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
144+
; CHECK-NEXT: ret
145+
%head = insertelement <4 x float> undef, float %b, i32 0
146+
%splat = shufflevector <4 x float> %head, <4 x float> undef, <4 x i32> zeroinitializer
147+
%v = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %splat)
148+
ret <4 x float> %v
149+
}
150+
151+
declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)
152+
153+
define <8 x float> @vfmax_v8f32_vv(<8 x float> %a, <8 x float> %b) {
154+
; CHECK-LABEL: vfmax_v8f32_vv:
155+
; CHECK: # %bb.0:
156+
; CHECK-NEXT: vsetivli a0, 8, e32,m2,ta,mu
157+
; CHECK-NEXT: vfmax.vv v8, v8, v10
158+
; CHECK-NEXT: ret
159+
%v = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b)
160+
ret <8 x float> %v
161+
}
162+
163+
define <8 x float> @vfmax_v8f32_vf(<8 x float> %a, float %b) {
164+
; CHECK-LABEL: vfmax_v8f32_vf:
165+
; CHECK: # %bb.0:
166+
; CHECK-NEXT: vsetivli a0, 8, e32,m2,ta,mu
167+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
168+
; CHECK-NEXT: ret
169+
%head = insertelement <8 x float> undef, float %b, i32 0
170+
%splat = shufflevector <8 x float> %head, <8 x float> undef, <8 x i32> zeroinitializer
171+
%v = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %splat)
172+
ret <8 x float> %v
173+
}
174+
175+
declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>)
176+
177+
define <16 x float> @vfmax_v16f32_vv(<16 x float> %a, <16 x float> %b) {
178+
; CHECK-LABEL: vfmax_v16f32_vv:
179+
; CHECK: # %bb.0:
180+
; CHECK-NEXT: vsetivli a0, 16, e32,m4,ta,mu
181+
; CHECK-NEXT: vfmax.vv v8, v8, v12
182+
; CHECK-NEXT: ret
183+
%v = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b)
184+
ret <16 x float> %v
185+
}
186+
187+
define <16 x float> @vfmax_v16f32_vf(<16 x float> %a, float %b) {
188+
; CHECK-LABEL: vfmax_v16f32_vf:
189+
; CHECK: # %bb.0:
190+
; CHECK-NEXT: vsetivli a0, 16, e32,m4,ta,mu
191+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
192+
; CHECK-NEXT: ret
193+
%head = insertelement <16 x float> undef, float %b, i32 0
194+
%splat = shufflevector <16 x float> %head, <16 x float> undef, <16 x i32> zeroinitializer
195+
%v = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %splat)
196+
ret <16 x float> %v
197+
}
198+
199+
declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
200+
201+
define <2 x double> @vfmax_v2f64_vv(<2 x double> %a, <2 x double> %b) {
202+
; CHECK-LABEL: vfmax_v2f64_vv:
203+
; CHECK: # %bb.0:
204+
; CHECK-NEXT: vsetivli a0, 2, e64,m1,ta,mu
205+
; CHECK-NEXT: vfmax.vv v8, v8, v9
206+
; CHECK-NEXT: ret
207+
%v = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
208+
ret <2 x double> %v
209+
}
210+
211+
define <2 x double> @vfmax_v2f64_vf(<2 x double> %a, double %b) {
212+
; CHECK-LABEL: vfmax_v2f64_vf:
213+
; CHECK: # %bb.0:
214+
; CHECK-NEXT: vsetivli a0, 2, e64,m1,ta,mu
215+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
216+
; CHECK-NEXT: ret
217+
%head = insertelement <2 x double> undef, double %b, i32 0
218+
%splat = shufflevector <2 x double> %head, <2 x double> undef, <2 x i32> zeroinitializer
219+
%v = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %splat)
220+
ret <2 x double> %v
221+
}
222+
223+
declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
224+
225+
define <4 x double> @vfmax_v4f64_vv(<4 x double> %a, <4 x double> %b) {
226+
; CHECK-LABEL: vfmax_v4f64_vv:
227+
; CHECK: # %bb.0:
228+
; CHECK-NEXT: vsetivli a0, 4, e64,m2,ta,mu
229+
; CHECK-NEXT: vfmax.vv v8, v8, v10
230+
; CHECK-NEXT: ret
231+
%v = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %a, <4 x double> %b)
232+
ret <4 x double> %v
233+
}
234+
235+
define <4 x double> @vfmax_v4f64_vf(<4 x double> %a, double %b) {
236+
; CHECK-LABEL: vfmax_v4f64_vf:
237+
; CHECK: # %bb.0:
238+
; CHECK-NEXT: vsetivli a0, 4, e64,m2,ta,mu
239+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
240+
; CHECK-NEXT: ret
241+
%head = insertelement <4 x double> undef, double %b, i32 0
242+
%splat = shufflevector <4 x double> %head, <4 x double> undef, <4 x i32> zeroinitializer
243+
%v = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %a, <4 x double> %splat)
244+
ret <4 x double> %v
245+
}
246+
247+
declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)
248+
249+
define <8 x double> @vfmax_v8f64_vv(<8 x double> %a, <8 x double> %b) {
250+
; CHECK-LABEL: vfmax_v8f64_vv:
251+
; CHECK: # %bb.0:
252+
; CHECK-NEXT: vsetivli a0, 8, e64,m4,ta,mu
253+
; CHECK-NEXT: vfmax.vv v8, v8, v12
254+
; CHECK-NEXT: ret
255+
%v = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %a, <8 x double> %b)
256+
ret <8 x double> %v
257+
}
258+
259+
define <8 x double> @vfmax_v8f64_vf(<8 x double> %a, double %b) {
260+
; CHECK-LABEL: vfmax_v8f64_vf:
261+
; CHECK: # %bb.0:
262+
; CHECK-NEXT: vsetivli a0, 8, e64,m4,ta,mu
263+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
264+
; CHECK-NEXT: ret
265+
%head = insertelement <8 x double> undef, double %b, i32 0
266+
%splat = shufflevector <8 x double> %head, <8 x double> undef, <8 x i32> zeroinitializer
267+
%v = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %a, <8 x double> %splat)
268+
ret <8 x double> %v
269+
}
270+
271+
declare <16 x double> @llvm.maxnum.v16f64(<16 x double>, <16 x double>)
272+
273+
define <16 x double> @vfmax_v16f64_vv(<16 x double> %a, <16 x double> %b) {
274+
; CHECK-LABEL: vfmax_v16f64_vv:
275+
; CHECK: # %bb.0:
276+
; CHECK-NEXT: vsetivli a0, 16, e64,m8,ta,mu
277+
; CHECK-NEXT: vfmax.vv v8, v8, v16
278+
; CHECK-NEXT: ret
279+
%v = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %a, <16 x double> %b)
280+
ret <16 x double> %v
281+
}
282+
283+
define <16 x double> @vfmax_v16f64_vf(<16 x double> %a, double %b) {
284+
; CHECK-LABEL: vfmax_v16f64_vf:
285+
; CHECK: # %bb.0:
286+
; CHECK-NEXT: vsetivli a0, 16, e64,m8,ta,mu
287+
; CHECK-NEXT: vfmax.vf v8, v8, fa0
288+
; CHECK-NEXT: ret
289+
%head = insertelement <16 x double> undef, double %b, i32 0
290+
%splat = shufflevector <16 x double> %head, <16 x double> undef, <16 x i32> zeroinitializer
291+
%v = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %a, <16 x double> %splat)
292+
ret <16 x double> %v
293+
}

0 commit comments

Comments
 (0)