@@ -79,8 +79,9 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
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// "zero_reg" definition.
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if (DI->getDef ()->isSubClassOf (" Register" ) ||
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DI->getDef ()->getName () == " zero_reg" ) {
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- OperandMap[BaseIdx + i].Kind = OpData::Reg;
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- OperandMap[BaseIdx + i].Data .Reg = DI->getDef ();
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+ auto &Entry = OperandMap[BaseIdx + i];
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+ Entry.Kind = OpData::Reg;
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+ Entry.Data .Reg = DI->getDef ();
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++OpsAdded;
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continue ;
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}
@@ -105,12 +106,14 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
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OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
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OpsAdded += Insn.Operands [i].MINumOperands ;
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} else if (const IntInit *II = dyn_cast<IntInit>(Dag->getArg (i))) {
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- OperandMap[BaseIdx + i].Kind = OpData::Imm;
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- OperandMap[BaseIdx + i].Data .Imm = II->getValue ();
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+ auto &Entry = OperandMap[BaseIdx + i];
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+ Entry.Kind = OpData::Imm;
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+ Entry.Data .Imm = II->getValue ();
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++OpsAdded;
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} else if (const auto *BI = dyn_cast<BitsInit>(Dag->getArg (i))) {
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- OperandMap[BaseIdx + i].Kind = OpData::Imm;
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- OperandMap[BaseIdx + i].Data .Imm = *BI->convertInitializerToInt ();
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+ auto &Entry = OperandMap[BaseIdx + i];
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+ Entry.Kind = OpData::Imm;
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+ Entry.Data .Imm = *BI->convertInitializerToInt ();
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++OpsAdded;
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} else if (const DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg (i))) {
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// Just add the operands recursively. This is almost certainly
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