[RISCV] Remove RISCVII::hasMergeOp. NFC

We can mostly get this from the operand info in MCInstrDesc.
The exception is the _TIED pseudos so I've added a new flag for those.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D152313

Author: topperc

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -58,7 +58,7 @@ enum {
   ConstraintShift = InstFormatShift + 5,
   VS2Constraint = 0b001 << ConstraintShift,
   VS1Constraint = 0b010 << ConstraintShift,
-  VMConstraint  = 0b100 << ConstraintShift,
+  VMConstraint = 0b100 << ConstraintShift,
   ConstraintMask = 0b111 << ConstraintShift,
 
   VLMulShift = ConstraintShift + 3,
@@ -68,15 +68,14 @@ enum {
   ForceTailAgnosticShift = VLMulShift + 3,
   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
 
-  // Does this instruction have a merge operand that must be removed when
-  // converting to MCInst. It will be the first explicit use operand. Used by
-  // RVV Pseudos.
-  HasMergeOpShift = ForceTailAgnosticShift + 1,
-  HasMergeOpMask = 1 << HasMergeOpShift,
+  // Is this a _TIED vector pseudo instruction. For these instructions we
+  // shouldn't skip the tied operand when converting to MC instructions.
+  IsTiedPseudoShift = ForceTailAgnosticShift + 1,
+  IsTiedPseudoMask = 1 << IsTiedPseudoShift,
 
   // Does this instruction have a SEW operand. It will be the last explicit
   // operand unless there is a vector policy operand. Used by RVV Pseudos.
-  HasSEWOpShift = HasMergeOpShift + 1,
+  HasSEWOpShift = IsTiedPseudoShift + 1,
   HasSEWOpMask = 1 << HasSEWOpShift,
 
   // Does this instruction have a VL operand. It will be the second to last
@@ -140,9 +139,9 @@ static inline VLMUL getLMul(uint64_t TSFlags) {
 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
   return TSFlags & ForceTailAgnosticMask;
 }
-/// \returns true if there is a merge operand for the instruction.
-static inline bool hasMergeOp(uint64_t TSFlags) {
-  return TSFlags & HasMergeOpMask;
+/// \returns true if this a _TIED pseudo.
+static inline bool isTiedPseudo(uint64_t TSFlags) {
+  return TSFlags & IsTiedPseudoMask;
 }
 /// \returns true if there is a SEW operand for the instruction.
 static inline bool hasSEWOp(uint64_t TSFlags) {
@@ -165,12 +164,6 @@ static inline bool usesMaskPolicy(uint64_t TSFlags) {
   return TSFlags & UsesMaskPolicyMask;
 }
 
-static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
-  assert(hasMergeOp(Desc.TSFlags));
-  assert(!Desc.isVariadic());
-  return Desc.getNumDefs();
-}
-
 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
   const uint64_t TSFlags = Desc.TSFlags;
   // This method is only called if we expect to have a VL operand, and all
@@ -199,9 +192,7 @@ static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
 // Is the first def operand tied to the first use operand. This is true for
 // vector pseudo instructions that have a merge operand for tail/mask
 // undisturbed. It's also true for vector FMA instructions where one of the
-// operands is also the destination register. This is different than
-// RISCVII::hasMergeOp which only indicates whether the tied operand from the
-// pseudoinstruction also exists on the MC layer instruction.
+// operands is also the destination register.
 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
   return Desc.getNumDefs() < Desc.getNumOperands() &&
          Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

@@ -631,10 +631,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
   assert(MF && "MBB expected to be in a machine function");
 
   const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   assert(TRI && "TargetRegisterInfo expected");
 
-  uint64_t TSFlags = MI->getDesc().TSFlags;
+  const MCInstrDesc &MCID = MI->getDesc();
+  uint64_t TSFlags = MCID.TSFlags;
   unsigned NumOps = MI->getNumExplicitOperands();
 
   // Skip policy, VL and SEW operands which are the last operands if present.
@@ -652,10 +654,17 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
     if (hasVLOutput && OpNo == 1)
       continue;
 
-    // Skip merge op. It should be the first operand after the result.
-    if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
-      assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
-      continue;
+    // Skip merge op. It should be the first operand after the defs.
+    if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
+      assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
+             "Expected tied to first def.");
+      const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
+      // Skip if the next operand in OutMI is not supposed to be tied. Unless it
+      // is a _TIED instruction.
+      if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) <
+              0 &&
+          !RISCVII::isTiedPseudo(TSFlags))
+        continue;
     }
 
     MCOperand MCOp;
@@ -704,7 +713,6 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
 
   // Unmasked pseudo instructions need to append dummy mask operand to
   // V instructions. All V instructions are modeled as the masked version.
-  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
   if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
     assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -190,8 +190,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
   bit ForceTailAgnostic = false;
   let TSFlags{11} = ForceTailAgnostic;
 
-  bit HasMergeOp = 0;
-  let TSFlags{12} = HasMergeOp;
+  bit IsTiedPseudo = 0;
+  let TSFlags{12} = IsTiedPseudo;
 
   bit HasSEWOp = 0;
   let TSFlags{13} = HasSEWOp;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1793,13 +1793,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
   }
 
   const uint64_t TSFlags = Desc.TSFlags;
-  if (RISCVII::hasMergeOp(TSFlags)) {
-    unsigned OpIdx = RISCVII::getMergeOpNum(Desc);
-    if (MI.findTiedOperandIdx(0) != OpIdx) {
-      ErrInfo = "Merge op improperly tied";
-      return false;
-    }
-  }
   if (RISCVII::hasVLOp(TSFlags)) {
     const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
     if (!Op.isImm() && !Op.isReg())  {