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[RISCV] Xqciint SystemRegs, Final Assembly Insts (llvm#130867)
This adds the Xqciint system registers from the Xqci-0.7 spec, as well as two leftover instructions: `qc.c.mret` and `qc.c.mnret` Co-authored-by: Sudharsan Veeravalli <[email protected]>
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7 files changed

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-28
lines changed

7 files changed

+718
-28
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -126,9 +126,9 @@ static const MCPhysReg FixedCSRFIMap[] = {
126126
static constexpr uint64_t QCIInterruptPushAmount = 96;
127127

128128
static const std::pair<MCPhysReg, int8_t> FixedCSRFIQCIInterruptMap[] = {
129-
/* -1 is a gap for mepc/qc.mnepc */
129+
/* -1 is a gap for mepc/mnepc */
130130
{/*fp*/ FPReg, -2},
131-
/* -3 is a gap for mcause */
131+
/* -3 is a gap for qc.mcause */
132132
{/*ra*/ RAReg, -4},
133133
/* -5 is reserved */
134134
{/*t0*/ RISCV::X5, -6},

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 33 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -700,38 +700,45 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
700700
} // Predicates = [HasVendorXqcicm, IsRV32]
701701

702702
let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {
703-
let mayLoad = 0, mayStore = 0 in {
704-
def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
705-
"qc.c.dir", "$rd"> {
706-
bits<5> rd;
707703

708-
let Inst{12} = 0b1;
709-
let Inst{11-7} = rd;
710-
let Inst{6-2} = 0b00000;
711-
}
704+
let mayLoad = 0, mayStore = 0 in {
705+
def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
706+
"qc.c.dir", "$rd"> {
707+
bits<5> rd;
708+
709+
let Inst{12} = 0b1;
710+
let Inst{11-7} = rd;
711+
let Inst{6-2} = 0b00000;
712+
}
713+
714+
def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
715+
def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
716+
717+
def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
718+
def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
719+
def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
712720

713-
def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
714-
def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
721+
def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
722+
def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
715723

716-
def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
717-
def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
718-
def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
724+
let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
725+
def QC_C_MRET : QCIRVInst16CI_NONE<0b10010, "qc.c.mret">;
726+
def QC_C_MNRET : QCIRVInst16CI_NONE<0b10011, "qc.c.mnret">;
727+
} // isBarrier = 1, isReturn = 1, isTerminator = 1
728+
} // mayLoad = 0, mayStore = 0
719729

720-
def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
721-
def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
722-
} // mayLoad = 0, mayStore = 0
730+
let mayLoad = 0, mayStore = 1,
731+
Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
732+
Defs = [X2, X8] in {
733+
def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
734+
def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
735+
} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
723736

724-
let mayLoad = 0, mayStore = 1,
725-
Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
726-
Defs = [X2, X8] in {
727-
def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
728-
def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
729-
} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
737+
let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
738+
Uses = [X2],
739+
Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
740+
def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
730741

731-
let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
732-
Uses = [X2],
733-
Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
734-
def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
735742
} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
736743

737744
let Predicates = [HasVendorXqcilo, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -471,3 +471,32 @@ def : SysReg<"sctrstatus", 0x14f>;
471471
def : SysReg<"sctrdepth", 0x15f>;
472472
def : SysReg<"vsctrctl", 0x24e>;
473473
def : SysReg<"mctrctl", 0x34e>;
474+
475+
//===-----------------------------------------------
476+
// Vendor CSRs
477+
//===-----------------------------------------------
478+
479+
// Xqciint
480+
let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
481+
def : SysReg<"qc.mmcr", 0x7C0>;
482+
def : SysReg<"qc.mntvec", 0x7C3>;
483+
def : SysReg<"qc.mstktopaddr", 0x7C4>;
484+
def : SysReg<"qc.mstkbottomaddr", 0x7C5>;
485+
def : SysReg<"qc.mthreadptr", 0x7C8>;
486+
def : SysReg<"qc.mcause", 0x7C9>;
487+
488+
foreach i = 0 - 7 in {
489+
def : SysReg<"qc.mclicip" # i, !add(0x7F0, i)>;
490+
def : SysReg<"qc.mclicie" # i, !add(0x7F8, i)>;
491+
}
492+
493+
foreach i = 0 - 31 in {
494+
def : SysReg<"qc.mclicilvl" # !if(!lt(i, 10), "0", "") # i,
495+
!add(0xBC0, i)>;
496+
}
497+
498+
foreach i = 0 - 3 in {
499+
def : SysReg<"qc.mwpstartaddr" # i, !add(0x7D0, i)>;
500+
def : SysReg<"qc.mwpendaddr" # i, !add(0x7D4, i)>;
501+
}
502+
} // FeatureVendorXqciint, isRV32Only

‎llvm/test/MC/RISCV/xqciint-csrs-invalid.s

Lines changed: 190 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,190 @@
1+
# Xqciint - Qualcomm uC Custom CSRs
2+
# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \
3+
# RUN: | FileCheck -check-prefixes=CHECK-FEATURE %s
4+
5+
csrrs t2, qc.mmcr, zero
6+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled
7+
8+
csrrs t2, qc.mntvec, zero
9+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled
10+
11+
csrrs t2, qc.mstktopaddr, zero
12+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstktopaddr' requires 'experimental-xqciint' to be enabled
13+
14+
csrrs t2, qc.mstkbottomaddr, zero
15+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstkbottomaddr' requires 'experimental-xqciint' to be enabled
16+
17+
csrrs t2, qc.mthreadptr, zero
18+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mthreadptr' requires 'experimental-xqciint' to be enabled
19+
20+
csrrs t2, qc.mcause, zero
21+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mcause' requires 'experimental-xqciint' to be enabled
22+
23+
csrrs t2, qc.mclicip0, zero
24+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip0' requires 'experimental-xqciint' to be enabled
25+
26+
csrrs t2, qc.mclicip1, zero
27+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip1' requires 'experimental-xqciint' to be enabled
28+
29+
csrrs t2, qc.mclicip2, zero
30+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip2' requires 'experimental-xqciint' to be enabled
31+
32+
csrrs t2, qc.mclicip3, zero
33+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip3' requires 'experimental-xqciint' to be enabled
34+
35+
csrrs t2, qc.mclicip4, zero
36+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip4' requires 'experimental-xqciint' to be enabled
37+
38+
csrrs t2, qc.mclicip5, zero
39+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip5' requires 'experimental-xqciint' to be enabled
40+
41+
csrrs t2, qc.mclicip6, zero
42+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip6' requires 'experimental-xqciint' to be enabled
43+
44+
csrrs t2, qc.mclicip7, zero
45+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip7' requires 'experimental-xqciint' to be enabled
46+
47+
csrrs t2, qc.mclicie0, zero
48+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie0' requires 'experimental-xqciint' to be enabled
49+
50+
csrrs t2, qc.mclicie1, zero
51+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie1' requires 'experimental-xqciint' to be enabled
52+
53+
csrrs t2, qc.mclicie2, zero
54+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie2' requires 'experimental-xqciint' to be enabled
55+
56+
csrrs t2, qc.mclicie3, zero
57+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie3' requires 'experimental-xqciint' to be enabled
58+
59+
csrrs t2, qc.mclicie4, zero
60+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie4' requires 'experimental-xqciint' to be enabled
61+
62+
csrrs t2, qc.mclicie5, zero
63+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie5' requires 'experimental-xqciint' to be enabled
64+
65+
csrrs t2, qc.mclicie6, zero
66+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie6' requires 'experimental-xqciint' to be enabled
67+
68+
csrrs t2, qc.mclicie7, zero
69+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie7' requires 'experimental-xqciint' to be enabled
70+
71+
csrrs t2, qc.mclicilvl00, zero
72+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl00' requires 'experimental-xqciint' to be enabled
73+
74+
csrrs t2, qc.mclicilvl01, zero
75+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl01' requires 'experimental-xqciint' to be enabled
76+
77+
csrrs t2, qc.mclicilvl02, zero
78+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl02' requires 'experimental-xqciint' to be enabled
79+
80+
csrrs t2, qc.mclicilvl03, zero
81+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl03' requires 'experimental-xqciint' to be enabled
82+
83+
csrrs t2, qc.mclicilvl04, zero
84+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl04' requires 'experimental-xqciint' to be enabled
85+
86+
csrrs t2, qc.mclicilvl05, zero
87+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl05' requires 'experimental-xqciint' to be enabled
88+
89+
csrrs t2, qc.mclicilvl06, zero
90+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl06' requires 'experimental-xqciint' to be enabled
91+
92+
csrrs t2, qc.mclicilvl07, zero
93+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl07' requires 'experimental-xqciint' to be enabled
94+
95+
csrrs t2, qc.mclicilvl08, zero
96+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl08' requires 'experimental-xqciint' to be enabled
97+
98+
csrrs t2, qc.mclicilvl09, zero
99+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl09' requires 'experimental-xqciint' to be enabled
100+
101+
csrrs t2, qc.mclicilvl10, zero
102+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl10' requires 'experimental-xqciint' to be enabled
103+
104+
csrrs t2, qc.mclicilvl11, zero
105+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl11' requires 'experimental-xqciint' to be enabled
106+
107+
csrrs t2, qc.mclicilvl12, zero
108+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl12' requires 'experimental-xqciint' to be enabled
109+
110+
csrrs t2, qc.mclicilvl13, zero
111+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl13' requires 'experimental-xqciint' to be enabled
112+
113+
csrrs t2, qc.mclicilvl14, zero
114+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl14' requires 'experimental-xqciint' to be enabled
115+
116+
csrrs t2, qc.mclicilvl15, zero
117+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl15' requires 'experimental-xqciint' to be enabled
118+
119+
csrrs t2, qc.mclicilvl16, zero
120+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl16' requires 'experimental-xqciint' to be enabled
121+
122+
csrrs t2, qc.mclicilvl17, zero
123+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl17' requires 'experimental-xqciint' to be enabled
124+
125+
csrrs t2, qc.mclicilvl18, zero
126+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl18' requires 'experimental-xqciint' to be enabled
127+
128+
csrrs t2, qc.mclicilvl19, zero
129+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl19' requires 'experimental-xqciint' to be enabled
130+
131+
csrrs t2, qc.mclicilvl20, zero
132+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl20' requires 'experimental-xqciint' to be enabled
133+
134+
csrrs t2, qc.mclicilvl21, zero
135+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl21' requires 'experimental-xqciint' to be enabled
136+
137+
csrrs t2, qc.mclicilvl22, zero
138+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl22' requires 'experimental-xqciint' to be enabled
139+
140+
csrrs t2, qc.mclicilvl23, zero
141+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl23' requires 'experimental-xqciint' to be enabled
142+
143+
csrrs t2, qc.mclicilvl24, zero
144+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl24' requires 'experimental-xqciint' to be enabled
145+
146+
csrrs t2, qc.mclicilvl25, zero
147+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl25' requires 'experimental-xqciint' to be enabled
148+
149+
csrrs t2, qc.mclicilvl26, zero
150+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl26' requires 'experimental-xqciint' to be enabled
151+
152+
csrrs t2, qc.mclicilvl27, zero
153+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl27' requires 'experimental-xqciint' to be enabled
154+
155+
csrrs t2, qc.mclicilvl28, zero
156+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl28' requires 'experimental-xqciint' to be enabled
157+
158+
csrrs t2, qc.mclicilvl29, zero
159+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl29' requires 'experimental-xqciint' to be enabled
160+
161+
csrrs t2, qc.mclicilvl30, zero
162+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl30' requires 'experimental-xqciint' to be enabled
163+
164+
csrrs t2, qc.mclicilvl31, zero
165+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl31' requires 'experimental-xqciint' to be enabled
166+
167+
csrrs t2, qc.mwpstartaddr0, zero
168+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr0' requires 'experimental-xqciint' to be enabled
169+
170+
csrrs t2, qc.mwpstartaddr1, zero
171+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr1' requires 'experimental-xqciint' to be enabled
172+
173+
csrrs t2, qc.mwpstartaddr2, zero
174+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr2' requires 'experimental-xqciint' to be enabled
175+
176+
csrrs t2, qc.mwpstartaddr3, zero
177+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr3' requires 'experimental-xqciint' to be enabled
178+
179+
csrrs t2, qc.mwpendaddr0, zero
180+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr0' requires 'experimental-xqciint' to be enabled
181+
182+
csrrs t2, qc.mwpendaddr1, zero
183+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr1' requires 'experimental-xqciint' to be enabled
184+
185+
csrrs t2, qc.mwpendaddr2, zero
186+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr2' requires 'experimental-xqciint' to be enabled
187+
188+
csrrs t2, qc.mwpendaddr3, zero
189+
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr3' requires 'experimental-xqciint' to be enabled
190+

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